ISE 12.1

Installation, licensing, and release information for ISE Design Suite 12

To communicate that Xilinx will be discontinuing the ModelSim™ Xilinx® Edition-III product, commonly known as MXE-III

The ISE Design Suite 12.1 Release Notes and Licensing Guide found on xilinx.com contains installation instructions, system requirements, and other general information.  This Known Issues Answer Record is a supplement to the release notes documentation and contains links to information on known issues in the design tools that might be resolved in future versions.

NOTE: For IP Known Issues, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

The ISE® 11.x, 12.x and 13.1 TRCE/Timing Analyzer tools do not correctly analyze certain control signals and address lines of the Virtex®-6 36Kb BRAM (RAMB36E1), 18Kb BRAM (RAMB18E1), and 18Kb FIFO (FIFO18E1) when used in SDP, TDP, or ECC modes, potentially resulting in unreported setup and hold time violations. The unreported violations can result in read and write errors in silicon and are not reported in the unconstrained path report section of the timing report.

A quick introduction to SmartXplorer and how its capabilities can be used to help achieve timing closure.

Design File(s):

• ug688.zip

A quick introduction to SmartXplorer and how its capabilities can be used to help achieve timing closure.

Design File(s):

• ug689.zip

The ISE® (ISim) In-Depth Tutorial provides Xilinx PLD designers with a detailed introduction of the ISE Simulator (ISim) software. After you have completed the tutorial, you will have a thorough understanding of how to analyze and debug your design via HDL simulation.

Design File(s):

• ug682.zip

Shows the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools.

Design File(s):

• wtut_edif.zip
• wtut_sc.zip
• wtut_ver.zip
• wtut_vhd.zip

This tutorial provides advice on how to use the Xilinx® Power Tools for accurate power consumption estimation. The tutorial focuses on a simple Virtex®-6 and Spartan®-6 design for use in both an XPower Estimator (XPE) spreadsheet and XPower Analyzer (XPA) to illustrate Power Tool usage on the designs. This tutorial also describes the power optimization options in the ISE implementations tools.

Design File(s):

• ug733.zip

This is the collection of manuals for the 12.1 ISE® software release. It includes all books and help for the 12.1 release.

This help system provides information about how to use the Xilinx® Integrated Software Environment.

Glossary for ISE Design Suite documentation

Designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs).

This document describes Xilinx® Synthesis Technology (XST) support for Hardware Description Language (HDL), Xilinx devices, and design constraints for the Xilinx ISE® Design Suite software

This book describes the command line programs for the Xilinx® development system. Formerly known as the Development System Reference Guide, the User Guide had a name refresh and is now the Command Line Tools User Guide.

The Xilinx® Constraints Guide describes constraints and attributes that can be attached to designs for Xilinx FPGA and CPLD devices.

This document describes how the Data2MEM software tool automates and simplifies setting the contents of Block RAM memory on Xilinx® FPGA family products.

Describes the XST synthesis tool, including instructions for running and controlling XST, discusses coding techniques for designing circuits using HDL, and gives guidelines to leverage built-in FPGA optimization techniques for Virtex®-6 and Spartan®-6.

Discusses processes and mechanisms available in the ISE® Design Suite and various Mentor Graphics tools to efficiently implement an FPGA on a PCB.

Discusses processes and mechanisms available in the ISE® Design Suite and various Cadence tools to efficiently implement an FPGA on a PCB.

This manual describes timing closure in high-performance Xilinx® FPGA designs

This document describes the Xilinx® ISim Hardware Description Language (HDL) simulator that enables you to perform functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs.

Describes primitives associated with the Spartan®-3 architecture for use in HDL designs. Details for each primitive include a circuit illustration, port and attribute tables, and instantiation code specific to the primitive.

Design File(s):

• Spartan-3 Library Guide 12.1 HDL Templates

Describes primitives associated with the Virtex®-5 architecture for use in HDL designs. Details for each primitive include a circuit illustration, port and attribute tables, and instantiation code specific to the primitive.

Design File(s):

• Virtex-5 Library Guide 12.1 HDL Templates

Describes primitives associated with the Virtex®-4 architecture for use in HDL designs. Details for each primitive include a circuit illustration, port and attribute tables, and instantiation code specific to the primitive.

Design File(s):

• Virtex-4 Library Guide 12.1 HDL Templates

Describes circuit design elements associated with the Spartan®-3 architecture for use in schematic designs. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes primitives associated with the Spartan®-3E architecture for use in HDL designs. Details for each primitive include a circuit illustration, port and attribute tables, and instantiation code specific to the primitive.

Design File(s):

• Spartan-3E Library Guide 12.1 HDL Templates

Describes design elements available for CPLD architectures. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Design File(s):

• CPLD All Library Guide 12.1 HDL Templates

Describes primitives associated with the Spartan®-3A and Spartan-3A DSP architectures for use in HDL designs. Details for each primitive include a circuit illustration, port and attribute tables, and instantiation code specific to the primitive.

Design File(s):

• Spartan-3A Library Guide 12.1 HDL Templates
• Spartan-3A DSP Library Guide 12.1 HDL Templates

Describes circuit design elements associated with the Virtex®-5 architecture. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes primitives associated with the Spartan®-6 architecture for use in HDL designs. Details for each primitive include a circuit illustration, port and attribute tables, and instantiation code specific to the primitive.

Design File(s):

• Spartan-6 Library Guide 12.1 HDL Templates

Describes primitives associated with the Virtex®-6 architecture for use in HDL designs. Details for each primitive include a circuit illustration, port and attribute tables, and instantiation code specific to the primitive.

Design File(s):

• Virtex-6 Library Guide 12.1 HDL Templates

Describes circuit design elements associated with the Virtex®-6 architecture for use in schematic designs. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Spartan®-6 architecture for use in schematic designs. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Spartan®-3E architectures for use in schematic designs. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Spartan®-3A and Spartan-3ADSP architectures for use in schematic designs. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Virtex®-4 architecture for use in schematic designs. Details for each element include schematic symbols, truth tables, and other information specific to the design element.