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PlanAhead 13.4

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PlanAhead - 13.4 Release Notes/Known Issues

DateName
01/18/2012 ISE Design Suite 13: Installation and Licensing Guide(PDF, ver 13.4, 1.01 MB )

Installation and licensing information for ISE Design Suite 13.

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01/25/2012 ISE Design Suite 13: Release Notes Guide(PDF, ver 13.4, 1.41 MB )

Release information and What's New for ISE® Design Suite 13

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PlanAhead - 13.4 Tutorials

DateName
01/16/2012 Quick Front-to-Back Overview Tutorial: PlanAhead Software(PDF, ver 13.4, 2.27 MB )

Provides a quick walk through of the front-to-back, RTL-to-bitstream design flow in the PlanAhead software.

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01/03/2012 PlanAhead Software Tutorial: Team Design(PDF, ver 13.4, 999 KB )

Provides an overview of the Team Design flow, in which you will complete a design acting as a team leader and various team members.

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01/18/2012 Partial Reconfiguration of a Processor Peripheral Tutorial: PlanAhead Software(PDF, ver 13.4, 1.53 MB )

Shows you how to develop a partial reconfiguration design using the Xilinx® Platform Studio (XPS) and the PlanAhead™ software.

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01/03/2012 Partial Reconfiguration Tutorial: PlanAhead Software(PDF, ver 13.4, 878 KB )

Shows you how to create a simple Partial Reconfiguration (PR) design from HDL synthesis through bit file generation and download.

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01/18/2012 PlanAhead Software Tutorial: Using Tcl and SDC Commands(PDF, ver 13.4, 423 KB )

Shows you how to use PlanAhead to write scripts with the Tool Command Language (Tcl) API and use Synopsys Design Constraint (SDC) commands.

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01/16/2012 Design Analysis and Floorplanning Tutorial: PlanAhead Software(PDF, ver 13.4, 2.67 MB )

Covers the analysis, floorplanning and implementation features of the PlanAhead software.

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01/18/2012 PlanAhead Software Tutorial: Debugging with ChipScope(PDF, ver 13.4, 691 KB )

Shows you how to use the Xilinx® PlanAhead™ software to debug designs using the ChipScope debugging tool.

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01/16/2012 RTL Design and IP Generation Tutorial: PlanAhead Software(PDF, ver 13.4, 1.72 MB )

Provides an overview of the RTL development and analysis environment, in which you import, compile, and explore an RTL design, and shows you how to browse the Xilinx® IP Catalog and customize and implement an IP core in the design.

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01/16/2012 I/O Pin Planning Tutorial: PlanAhead Software(PDF, ver 13.4, 3.71 MB )

Shows you the Xilinx® PlanAhead™ software capabilities and benefits to performing I/O pin assignments for FPGA devices.

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01/03/2012 Design Preservation Tutorial: PlanAhead Software(PDF, ver 13.4, 594 KB )

Provides an overview of the Design Preservation flow, in which you learn how to work with partitions in a design.

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PlanAhead - 13.4 User Guides

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01/18/2012 PlanAhead User Guide(PDF, ver 13.4, 18.32 MB )

Describes the PlanAhead™ tool, its user interface, and its features.

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01/18/2012 PlanAhead Tcl Command Reference Guide(PDF, ver 13.4, 5.96 MB )

List and description of Tcl commands available in the PlanAhead™ tool, including SDC and XDC constraints commands.

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03/01/2011 Floorplanning Methodology Guide(PDF, ver 13.1, 1.11 MB )

Covers the basics of floorplanning and floorplanning techniques, and presents two approaches to floorplanning that can help a design meet timing more consistently.

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01/18/2012 Hierarchical Design Methodology Guide(PDF, ver 13.4, 1.96 MB )

Gives an overview of the Hierarchical Design methodologies in the Xilinx® software, and provides a detailed description of how to design using partitions in a Design Preservation flow.

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01/18/2012 Partial Reconfiguration User Guide(PDF, ver 13.4, 4.52 MB )

Describes how to create and implement an FPGA design that is partially reconfigurable using a modular design technique called Partitioning.

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01/18/2012 Large FPGA Methodology Guide(PDF, ver 13.4, 1.68 MB )

The Large FPGA Methodology Guide (UG782) addresses designs targeting large FPGA devices. This guide includes, but is not limited to, designs using Stacked Silicon Interconnect (SSI) technology.

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07/06/2011 Pin Planning Methodology Guide(PDF, ver 13.2, 296 KB )

Methodology for pin planning in the PlanAhead™ tool

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03/01/2011 Power Methodology Guide(PDF, ver 13.1, 2.13 MB )

Provides a complete view of the FPGA internal factors and system dependencies which influence the device thermal and supply power requirements. Presents methodologies, tips, and techniques to most efficiently monitor and optimize power at every stage in the design process using the comprehensive Xilinx toolset: XPower Estimator, XPower Analyzer, ISE, and PlanAhead.

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