Filter

FPGAs have been used in DSP applications for years; more recently FPGAs have been emerging as ideal co-processors for standard DSP devices. FPGAs provide tremendous computational throughput by using highly parallel architectures, and are hardware reconfigurable, allowing the designer to develop customized architectures for ideal implementation of their algorithms. The new generation of FPGAs developed using 90-nm process technology provide the designer with an even more cost-effective solution. This white paper takes a look at some common high-performance DSP functions and calculates their effective implementation costs.

Traditionally, digital signal processing (DSP) algorithms are implemented using general-purpose programmable DSP chips for low-rate applications. Alternatively, special-purpose, fixed function DSP chipsets and application-specific integrated circuits (ASICs) are used for high-performance applications. Technological advancements by Xilinx in Field Programmable Gate Arrays (FPGAs) in the past 15 years have opened new paths for DSP design engineers. The most common digital building blocks, like serial peripherals, DMA controllers, PCI controllers, and synthesizable processors, are all readily realizable using a Spartan-II device. In fact, all the most basic operations performed by analog or digital electronic devices—filtering, amplification, modulation, storage, and computation—can be implemented with Spartan-II.

Virtex™-E Extended Memory (Virtex™-EM) FPGA devices offer over a million bits of block RAM and up to 300 Kb of distributed RAM in a single high-performance device. This is ideal for high-bandwidth video applications where complex digital filtering logic can operate on several lines of pixel data on-chip. The reconfigurable nature of Virtex-EM devices offers designers a flexible platform for optimizing Digital Signal Processor (DSP) parameters and algorithms throughout the design and preproduction cycle, as well as when the devices are in the field. This reprogrammability allows periodic optimization of proprietary algorithms in such applications as MPEG compression.

This application note describes a high-speed, reconfigurable, full-precision Transposed Form FIR filter design implemented in the Virtex™ and Virtex™-II series and Spartan™-II family of FPGAs. The VHDL reference design provided with this application note is easily modified to change filter parameters including coefficients and the number of taps. By illustrating a design methodology for digital filters, the advantages of using FPGAs for digital signal processing applications (DSP) are emphasized. The CORE Generator™ tool provides a preoptimized alternative solution to this reference design.

Code Division Multiple Access (CDMA) is a rapidly expanding data transmission technique in the emerging Universal Mobile Telecommunications System (UMTS). This application note describes the implementation of a CDMA matched filter using the architectural features of the Virtex™ series, Virtex™-II series, and Spartan™-II family of devices.

This application note demonstrates how to efficiently implement Digitial Up and Down Converters(DUC/DDC) by leveraging the Xilinx DSP IP portfolio. Two example DUC/DDC designs are provided for UMTS and CDMA2000 in both Spartan™-DSP and Virtex™-5 FPGAs.