MicroBlaze Debug Module LogiCORE IP Product Guide (PG115) - 3.2 English

Document ID: PG115
Release Date: 2021-01-21
Version: 3.2 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Licensing and Ordering
Product Specification
Standards
Performance and Resource Utilization
Port Descriptions
AXI4-Lite Slave Interface Signals
AXI4 Master Interface Signals
LMB Master Interface Signals
MicroBlaze Serial Debug Interface Signals
MicroBlaze Parallel Debug Interface Signals
MicroBlaze Other Debug Interface Signals
External Cross Trigger Signals
MicroBlaze Trace Core Interface Signals
External BSCAN Interface Signals
AXI4-Stream Trace Output
External Trace Output
Register Space
AXI Slave Register Space
UART Receive FIFO Register (UART_RX_FIFO)
UART Transmit FIFO Register (UART_TX_FIFO)
UART Status Register (UART_STATUS)
UART Control Register (UART_CTRL)
Debug Register Access Status Register (DBG_STATUS)
Debug Register Access Control Register (DBG_CTRL)
Debug Register Access Data Register (DBG_DATA)
Debug Register Access Locking Register (DBG_LOCK)
MDM Core Interrupts
Debug Register Space
MDM Core User-Accessible Debug Registers
MDM Configuration Debug Register
MDM Extended Configuration Debug Register
Which MicroBlaze Debug Register
External Cross Trigger Control Debug Register
Cross Trigger Control Debug Register
Cross Trigger Status Debug Register
External Trace Control Debug Register
AXI4-Stream Trace Control Debug Register
AXI4-Master Trace Status Debug Register
AXI4-Master Trace Current Address Debug Register
AXI4-Master Trace Buffer Low Address Debug Register
AXI4-Master Trace Buffer High Address Debug Register
AXI4-Master Trace Control Debug Register
Trace Packet Definition
External Trace and AXI4-Master Trace Packets
AXI4-Stream Trace Packets
Designing with the Core
General Design Guidelines
Multiprocessor Designs
Discrete Outputs
Memory Access
Parallel Debug
Xilinx Virtual Cable
Clocking
Resets
Debug Register Access Sequence
Cross Trigger Programming
External Trace Connection
Protocol Description
Design Flow Steps
Customizing and Generating the Core
Parameter Values
User Parameters
Allowable Parameter Combinations
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Hardware Debug
General Checks
Interface Debug
AXI4-Lite Interfaces
Application Software Development
Device Drivers
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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