Resource Utilization for AXI Bridge for PCI Express Gen3 Subsystem v3.0

Vivado Design Suite Release 2018.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku040 ffva1156 -2 xcku040_ffva1156_2_x1g1 X1 2.5_GT/s refclk=100 sys_clk_gt=100 3445 3204 1475 0 7 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x1g2 X1 5.0_GT/s refclk=100 sys_clk_gt=100 3442 3338 1446 0 7 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x1g3 X1 8.0_GT/s refclk=100 sys_clk_gt=100 3439 3338 1446 0 7 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x2g1 X2 2.5_GT/s refclk=100 sys_clk_gt=100 3526 3365 1523 0 7 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x2g2 X2 5.0_GT/s refclk=100 sys_clk_gt=100 3508 3610 1490 0 7 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x2g3 X2 8.0_GT/s refclk=100 sys_clk_gt=100 4322 4705 2008 0 11 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x4g1 X4 2.5_GT/s refclk=100 sys_clk_gt=100 3667 3687 1609 0 7 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x4g2 X4 5.0_GT/s refclk=100 sys_clk_gt=100 4062 4507 1764 0 11 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x4g3 X4 8.0_GT/s refclk=100 sys_clk_gt=100 5018 6635 2318 0 19 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x8g1 X8 2.5_GT/s refclk=100 sys_clk_gt=100 4403 4684 1986 0 11 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x8g2 X8 5.0_GT/s refclk=100 sys_clk_gt=100 4750 6254 2151 0 19 12 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x8g3 X8 8.0_GT/s refclk=100 sys_clk_gt=100 4819 6254 2164 0 19 12 PRODUCTION 1.24.01 01-12-2017

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1761 -2 fcsvrg1x1xc7vx690tffg17611_0 X1 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4090 3544 1871 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg1x2xc7vx690tffg17611_0 X2 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4485 3949 2069 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg1x4xc7vx690tffg17611_0 X4 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5323 4759 2474 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg1x8xc7vx690tffg17611_0 X8 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7267 6825 3415 0 15 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x1xc7vx690tffg17611_0 X1 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4082 3544 1867 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x2xc7vx690tffg17611_0 X2 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4471 3949 2054 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x4xc7vx690tffg17611_0 X4 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5500 5118 2580 0 15 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x8xc7vx690tffg17611_0 X8 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7666 7477 3575 0 23 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x1xc7vx690tffg17611_0 X1 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4005 3540 1876 0 7 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x2xc7vx690tffg17611_0 X2 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4646 4297 2210 0 11 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x4xc7vx690tffg17611_0 X4 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5932 5750 2737 0 19 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x8xc7vx690tffg17611_0 X8 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7670 7478 3594 0 19 12 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x1g1 X1 2.5_GT/s refclk=100 sys_clk_gt=100 3448 3204 1440 0 7 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x1g2 X1 5.0_GT/s refclk=100 sys_clk_gt=100 3436 3338 1443 0 7 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x1g3 X1 8.0_GT/s refclk=100 sys_clk_gt=100 3431 3338 1440 0 7 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x2g1 X2 2.5_GT/s refclk=100 sys_clk_gt=100 3524 3365 1489 0 7 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x2g2 X2 5.0_GT/s refclk=100 sys_clk_gt=100 3513 3610 1498 0 7 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x2g3 X2 8.0_GT/s refclk=100 sys_clk_gt=100 4320 4705 1980 0 11 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x4g1 X4 2.5_GT/s refclk=100 sys_clk_gt=100 3677 3687 1597 0 7 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x4g2 X4 5.0_GT/s refclk=100 sys_clk_gt=100 4070 4507 1766 0 11 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x4g3 X4 8.0_GT/s refclk=100 sys_clk_gt=100 5015 6635 2405 0 19 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x8g1 X8 2.5_GT/s refclk=100 sys_clk_gt=100 4393 4684 1970 0 11 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x8g2 X8 5.0_GT/s refclk=100 sys_clk_gt=100 4756 6254 2135 0 19 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x8g3 X8 8.0_GT/s refclk=100 sys_clk_gt=100 4816 6264 2151 0 19 12 PRODUCTION 1.25.01 01-12-2017

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