Resource Utilization for AXI Bridge for PCI Express Gen3 Subsystem v3.0

Vivado Design Suite Release 2017.3

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku040 ffva1156 -2 xcku040_ffva1156_2_x1g1 X1 2.5_GT/s refclk=100 sys_clk_gt=100 3367 3194 1442 0 7 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x1g2 X1 5.0_GT/s refclk=100 sys_clk_gt=100 3437 3328 1441 0 7 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x1g3 X1 8.0_GT/s refclk=100 sys_clk_gt=100 3374 3328 1422 0 7 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x2g1 X2 2.5_GT/s refclk=100 sys_clk_gt=100 3433 3353 1482 0 7 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x2g2 X2 5.0_GT/s refclk=100 sys_clk_gt=100 3503 3598 1489 0 7 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x2g3 X2 8.0_GT/s refclk=100 sys_clk_gt=100 4052 4701 1839 0 11 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x4g1 X4 2.5_GT/s refclk=100 sys_clk_gt=100 3580 3671 1572 0 7 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x4g2 X4 5.0_GT/s refclk=100 sys_clk_gt=100 3882 4499 1749 0 11 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x4g3 X4 8.0_GT/s refclk=100 sys_clk_gt=100 4988 6618 2270 0 19 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x8g1 X8 2.5_GT/s refclk=100 sys_clk_gt=100 4168 4668 1906 0 11 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x8g2 X8 5.0_GT/s refclk=100 sys_clk_gt=100 4885 6222 2102 0 19 12 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 xcku040_ffva1156_2_x8g3 X8 8.0_GT/s refclk=100 sys_clk_gt=100 4926 6222 2104 0 19 12 PRODUCTION 1.23 03-22-2017

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1761 -2 fcsvrg1x1xc7vx690tffg17611_0 X1 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4049 3532 1826 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg1x2xc7vx690tffg17611_0 X2 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4459 3937 2013 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg1x4xc7vx690tffg17611_0 X4 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5324 4747 2440 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg1x8xc7vx690tffg17611_0 X8 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7335 6813 3394 0 15 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x1xc7vx690tffg17611_0 X1 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4094 3532 1818 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x2xc7vx690tffg17611_0 X2 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4507 3937 2010 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x4xc7vx690tffg17611_0 X4 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5534 5099 2551 0 15 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg2x8xc7vx690tffg17611_0 X8 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7763 7448 3509 0 23 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x1xc7vx690tffg17611_0 X1 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 3964 3528 1821 0 7 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x2xc7vx690tffg17611_0 X2 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4643 4285 2178 0 11 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x4xc7vx690tffg17611_0 X4 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5995 5731 2720 0 19 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 fcsvrg3x8xc7vx690tffg17611_0 X8 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7788 7444 3577 0 19 12 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x1g1 X1 2.5_GT/s refclk=100 sys_clk_gt=100 3371 3194 1421 0 7 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x1g2 X1 5.0_GT/s refclk=100 sys_clk_gt=100 3435 3328 1449 0 7 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x1g3 X1 8.0_GT/s refclk=100 sys_clk_gt=100 3375 3328 1432 0 7 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x2g1 X2 2.5_GT/s refclk=100 sys_clk_gt=100 3441 3353 1459 0 7 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x2g2 X2 5.0_GT/s refclk=100 sys_clk_gt=100 3505 3598 1475 0 7 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x2g3 X2 8.0_GT/s refclk=100 sys_clk_gt=100 4045 4701 1829 0 11 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x4g1 X4 2.5_GT/s refclk=100 sys_clk_gt=100 3580 3671 1587 0 7 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x4g2 X4 5.0_GT/s refclk=100 sys_clk_gt=100 3882 4499 1734 0 11 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x4g3 X4 8.0_GT/s refclk=100 sys_clk_gt=100 4980 6618 2252 0 19 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x8g1 X8 2.5_GT/s refclk=100 sys_clk_gt=100 4160 4668 1946 0 11 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x8g2 X8 5.0_GT/s refclk=100 sys_clk_gt=100 4881 6222 2053 0 19 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -2 pcie3_xcvu09566180_x8g3 X8 8.0_GT/s refclk=100 sys_clk_gt=100 4928 6222 2087 0 19 12 PRODUCTION 1.24 03-22-2017

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