Resource Utilization for FIFO Generator v13.2

Vivado Design Suite Release 2017.3

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
Fifo_Implementation
INTERFACE_TYPE
Performance_Options
Input_Data_Width
Input_Depth
Programmable_Full_Type
Programmable_Empty_Type
Clock_Type_AXI
TDATA_NUM_BYTES
TUSER_WIDTH
FIFO_Implementation_axis
Input_Depth_axis
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbg484 -1 fifo_con10_v7 AXI_MEMORY_MAPPED Common_Clock s_aclk=100 283 632 164 0 4 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con11_v7 AXI_MEMORY_MAPPED Independent_Clock m_aclk=100 s_aclk=100 389 1010 197 0 4 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con1_1_p_v7 Common_Clock_Block_RAM Native 16 4096 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 87 93 33 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con1_1_v7 Common_Clock_Block_RAM Native 16 4096 clk=100 33 52 6 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con1_p_v7 Common_Clock_Block_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 86 72 33 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con1_v7 Common_Clock_Block_RAM Native 16 512 clk=100 40 40 16 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con2_1_p_v7 Independent_Clocks_Block_RAM Native 16 4096 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 122 240 77 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con2_1_v7 Independent_Clocks_Block_RAM Native 16 4096 rd_clk=100 wr_clk=100 81 202 46 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con2_p_v7 Independent_Clocks_Block_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 111 190 67 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con2_v7 Independent_Clocks_Block_RAM Native 16 512 rd_clk=100 wr_clk=100 77 161 43 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con3_1_p_v7 Common_Clock_Distributed_RAM Native 16 64 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 77 67 47 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con3_1_v7 Common_Clock_Distributed_RAM Native 16 64 clk=100 48 44 30 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con3_p_v7 Common_Clock_Distributed_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 301 88 51 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con3_v7 Common_Clock_Distributed_RAM Native 16 512 clk=100 256 56 30 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con4_p_v7 Common_Clock_Shift_Register Native 16 64 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 129 61 53 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con4_v7 Common_Clock_Shift_Register Native 16 64 clk=100 97 38 31 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con5_p_v7 Common_Clock_Shift_Register Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 758 94 74 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con5_v7 Common_Clock_Shift_Register Native 16 512 clk=100 705 62 49 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con6_1_fwft_v7 Independent_Clocks_Builtin_FIFO Native First_Word_Fall_Through 8 16384 rd_clk=1 wr_clk=1 9 10 3 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con6_1_std_v7 Independent_Clocks_Builtin_FIFO Native Standard_FIFO 8 16384 rd_clk=1 wr_clk=1 9 10 3 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con6_fwft_v7 Independent_Clocks_Builtin_FIFO Native First_Word_Fall_Through 72 512 rd_clk=1 wr_clk=1 3 10 3 0 1 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con6_std_v7 Independent_Clocks_Builtin_FIFO Native Standard_FIFO 72 512 rd_clk=1 wr_clk=1 3 10 3 0 1 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con7_1_fwft_v7 Common_Clock_Builtin_FIFO Native First_Word_Fall_Through 8 16384 clk=100 9 18 5 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con7_1_std_v7 Common_Clock_Builtin_FIFO Native Standard_FIFO 8 16384 clk=100 7 14 2 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con7_fwft_v7 Common_Clock_Builtin_FIFO Native First_Word_Fall_Through 72 512 clk=100 4 12 3 0 1 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con7_std_v7 Common_Clock_Builtin_FIFO Native Standard_FIFO 72 512 clk=100 3 10 3 0 1 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con8_br_1_v7 AXI_STREAM Common_Clock 1 4 Common_Clock_Block_RAM 4096 s_aclk=100 46 89 14 0 1 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con8_br_v7 AXI_STREAM Common_Clock 1 4 Common_Clock_Block_RAM 512 s_aclk=100 55 77 28 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con8_dr_1_v7 AXI_STREAM Common_Clock 1 4 Common_Clock_Distributed_RAM 64 s_aclk=100 52 69 33 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con8_dr_v7 AXI_STREAM Common_Clock 1 4 Common_Clock_Distributed_RAM 512 s_aclk=100 213 168 130 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con9_br_1_v7 AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Block_RAM 4096 m_aclk=100 s_aclk=100 88 222 51 0 1 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con9_br_v7 AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Block_RAM 512 m_aclk=100 s_aclk=100 84 181 55 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con9_dr_1_v7 AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Distributed_RAM 64 m_aclk=100 s_aclk=100 69 138 40 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_con9_dr_v7 AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Distributed_RAM 512 m_aclk=100 s_aclk=100 239 264 62 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_conx_1_p_v7 Independent_Clocks_Distributed_RAM Native 16 64 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 90 142 44 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_conx_1_v7 Independent_Clocks_Distributed_RAM Native 16 64 rd_clk=100 wr_clk=100 66 122 34 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_conx_p_v7 Independent_Clocks_Distributed_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 317 190 81 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbg484 -1 fifo_conx_v7 Independent_Clocks_Distributed_RAM Native 16 512 rd_clk=100 wr_clk=100 286 161 61 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
Fifo_Implementation
INTERFACE_TYPE
Performance_Options
Input_Data_Width
Input_Depth
Programmable_Full_Type
Programmable_Empty_Type
Clock_Type_AXI
TDATA_NUM_BYTES
TUSER_WIDTH
FIFO_Implementation_axis
Input_Depth_axis
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flvd1517 -1 fifo_con1 Common_Clock_Block_RAM Native 16 512 clk=100 44 42 17 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con10 AXI_MEMORY_MAPPED Common_Clock s_aclk=100 171 363 97 0 5 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con11 AXI_MEMORY_MAPPED Independent_Clock m_aclk=100 s_aclk=100 199 516 92 0 5 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con1_1 Common_Clock_Block_RAM Native 16 4096 clk=100 36 54 5 0 2 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con1_1_p Common_Clock_Block_RAM Native 16 4096 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 90 94 37 0 2 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con1_p Common_Clock_Block_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 88 73 36 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con2 Independent_Clocks_Block_RAM Native 16 512 rd_clk=100 wr_clk=100 78 162 47 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con2_1 Independent_Clocks_Block_RAM Native 16 4096 rd_clk=100 wr_clk=100 81 203 46 0 2 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con2_1_p Independent_Clocks_Block_RAM Native 16 4096 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 121 241 75 0 2 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con2_p Independent_Clocks_Block_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 111 191 68 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con3 Common_Clock_Distributed_RAM Native 16 512 clk=100 241 57 32 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con3_1 Common_Clock_Distributed_RAM Native 16 64 clk=100 49 45 32 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con3_1_p Common_Clock_Distributed_RAM Native 16 64 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 79 68 42 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con3_p Common_Clock_Distributed_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants clk=100 287 89 53 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con4 Common_Clock_Shift_Register Native 16 64 clk=100 110 39 33 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con5 Common_Clock_Shift_Register Native 16 512 clk=100 716 53 50 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con6_1_fwft Independent_Clocks_Builtin_FIFO Native First_Word_Fall_Through 8 16384 rd_clk=1 wr_clk=1 0 2 0 0 4 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con6_fwft Independent_Clocks_Builtin_FIFO Native First_Word_Fall_Through 72 512 rd_clk=1 wr_clk=1 0 0 0 0 1 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con7_1_fwft Common_Clock_Builtin_FIFO Native First_Word_Fall_Through 8 16384 clk=100 0 0 0 0 4 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con7_1_std Common_Clock_Builtin_FIFO Native Standard_FIFO 8 16384 clk=100 0 0 0 0 4 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con7_fwft Common_Clock_Builtin_FIFO Native First_Word_Fall_Through 72 512 clk=100 0 0 0 0 1 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con8_bi AXI_STREAM Common_Clock 1 4 Common_Clock_Builtin_FIFO 512 s_aclk=100 3 2 0 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con8_bi_1 AXI_STREAM Common_Clock 1 4 Common_Clock_Builtin_FIFO 4096 s_aclk=100 3 2 0 0 2 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con8_br AXI_STREAM Common_Clock 1 4 Common_Clock_Block_RAM 512 s_aclk=100 52 77 24 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con8_br_1 AXI_STREAM Common_Clock 1 4 Common_Clock_Block_RAM 4096 s_aclk=100 46 89 14 0 1 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con8_dr AXI_STREAM Common_Clock 1 4 Common_Clock_Distributed_RAM 512 s_aclk=100 209 168 130 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con8_dr_1 AXI_STREAM Common_Clock 1 4 Common_Clock_Distributed_RAM 64 s_aclk=100 52 69 31 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con9_bi AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Builtin_FIFO 512 m_aclk=100 s_aclk=100 3 2 0 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con9_bi_1 AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Builtin_FIFO 4096 m_aclk=100 s_aclk=100 3 2 0 0 2 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con9_br AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Block_RAM 512 m_aclk=100 s_aclk=100 84 181 56 0 0 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con9_br_1 AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Block_RAM 4096 m_aclk=100 s_aclk=100 88 222 52 0 1 1 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con9_dr AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Distributed_RAM 512 m_aclk=100 s_aclk=100 235 264 66 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_con9_dr_1 AXI_STREAM Independent_Clock 1 4 Independent_Clocks_Distributed_RAM 64 m_aclk=100 s_aclk=100 68 138 40 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_conx Independent_Clocks_Distributed_RAM Native 16 512 rd_clk=100 wr_clk=100 268 161 59 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_conx_1 Independent_Clocks_Distributed_RAM Native 16 64 rd_clk=100 wr_clk=100 66 122 37 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_conx_1_p Independent_Clocks_Distributed_RAM Native 16 64 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 88 142 46 0 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flvd1517 -1 fifo_conx_p Independent_Clocks_Distributed_RAM Native 16 512 Multiple_Programmable_Full_Threshold_Input_Ports Multiple_Programmable_Empty_Threshold_Constants rd_clk=100 wr_clk=100 300 190 84 0 0 0 PRODUCTION 1.24 03-22-2017

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