Resource Utilization for JESD204 v7.2

Vivado Design Suite Release 2018.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTPE2_CHANNEL Speedfile Status
xc7a200t ffg1156 -2 GTPE2_rx_1lane 0 1 1024 0 4 100 rx_core_clk=78 s_axi_aclk=100 1433 1171 499 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_rx_2lane 0 2 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 2249 1933 732 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_rx_3lane 0 3 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 3242 2695 973 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_rx_4lane 0 4 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 4119 3456 1204 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_rx_5lane 0 5 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 5011 4218 1424 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_rx_6lane 0 6 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 5968 4979 1674 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_rx_7lane 0 7 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 6928 5740 1911 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_rx_8lane 0 8 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 7797 6501 2152 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_1lane 1 1 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1285 912 466 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_2lane 1 2 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1491 1179 559 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_3lane 1 3 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1742 1430 663 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_4lane 1 4 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1973 1681 754 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_5lane 1 5 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2215 1932 850 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_6lane 1 6 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2457 2183 944 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_7lane 1 7 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2703 2434 1041 0 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a200t ffg1156 -2 GTPE2_tx_8lane 1 8 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2946 2685 1149 0 0 0 0 PRODUCTION 1.22 2018-03-21

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTXE2_CHANNEL BUFG Speedfile Status
xc7k325t ffg900 -2 GTXE2_rx_1lane 0 1 1024 0 0 100 rx_core_clk=156 s_axi_aclk=100 1448 1193 501 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 2258 1955 739 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 3244 2717 968 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 4127 3478 1201 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 5017 4240 1429 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 5979 5001 1683 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 6928 5762 1914 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 7807 6523 2151 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_1lane 1 1 1 false false false 0 0 100 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/RXOUTCLK=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/RXOUTCLKFABRIC=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/TXOUTCLK=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/TXOUTCLKFABRIC=156 refclk_p=156 s_axi_aclk=100 1525 1265 598 0 0 0 1 1 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1501 1201 557 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1746 1452 665 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1989 1703 767 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2229 1954 835 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2467 2205 958 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2714 2456 1069 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2955 2707 1150 0 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTHE3_CHANNEL Speedfile Status
xcku040 ffva1156 -2 GTHE3_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1388 1171 488 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 2193 1933 749 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 3170 2695 1032 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4019 3456 1268 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4884 4218 1524 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5808 4979 1774 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 6678 5740 2092 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 7560 6501 2283 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_1lane 1 1 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1290 921 440 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1518 1172 535 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1748 1423 616 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1978 1674 713 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2213 1925 823 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2453 2176 911 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2685 2427 994 0 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 GTHE3_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2927 2678 1090 0 0 0 0 PRODUCTION 1.24.01 01-12-2017

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTHE2_CHANNEL Speedfile Status
xc7vx690t ffg1761 -2 GTHE2_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1436 1171 498 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 2252 1933 738 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 3246 2695 975 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4122 3456 1211 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5008 4218 1429 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5966 4979 1672 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 6924 5740 1911 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 7801 6501 2151 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_1lane 1 1 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1276 912 458 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1490 1179 552 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1740 1430 651 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1972 1681 758 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2216 1932 844 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2456 2183 951 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2700 2434 1042 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2943 2685 1142 0 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTYE4_CHANNEL Speedfile Status
xcvu3p ffvc1517 -2 GTYE4_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1386 1171 487 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_rx_2lane 0 2 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 2194 1933 755 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_rx_3lane 0 3 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 3169 2695 1011 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_rx_4lane 0 4 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4022 3456 1286 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_rx_5lane 0 5 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4884 4218 1498 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_rx_6lane 0 6 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 5807 4979 1798 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_rx_7lane 0 7 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 6678 5740 2077 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_rx_8lane 0 8 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 7562 6501 2329 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_1lane 1 1 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1290 921 431 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_2lane 1 2 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1516 1172 537 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_3lane 1 3 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1751 1423 638 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_4lane 1 4 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1979 1674 720 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_5lane 1 5 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2214 1925 828 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_6lane 1 6 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2451 2176 905 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_7lane 1 7 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2686 2427 1003 0 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu3p ffvc1517 -2 GTYE4_tx_8lane 1 8 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2926 2678 1090 0 0 0 0 PRODUCTION 1.20 05-21-2018

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTHE4_CHANNEL Speedfile Status
xczu9eg ffvb1156 -1 GTHE4_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1389 1171 489 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_rx_2lane 0 2 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 2196 1933 755 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_rx_3lane 0 3 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 3169 2695 1030 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_rx_4lane 0 4 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4025 3456 1301 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_rx_5lane 0 5 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4883 4218 1528 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_rx_6lane 0 6 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 5809 4979 1805 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_rx_7lane 0 7 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 6678 5740 2083 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_rx_8lane 0 8 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 7556 6501 2332 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_1lane 1 1 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1290 921 437 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_2lane 1 2 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1516 1172 536 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_3lane 1 3 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1750 1423 622 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_4lane 1 4 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1979 1674 730 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_5lane 1 5 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2214 1925 828 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_6lane 1 6 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2451 2176 902 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_7lane 1 7 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2687 2427 998 0 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 GTHE4_tx_8lane 1 8 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2929 2678 1103 0 0 0 0 PRODUCTION 1.20 05-21-2018

COPYRIGHT

Copyright 2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.