Resource Utilization for JESD204 v7.2

Vivado Design Suite Release 2017.3

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTPE2_CHANNEL Speedfile Status
xc7a200t ffg1156 -2 GTPE2_rx_1lane 0 1 1024 0 4 100 rx_core_clk=78 s_axi_aclk=100 1442 1171 484 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_rx_2lane 0 2 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 2247 1933 725 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_rx_3lane 0 3 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 3240 2695 943 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_rx_4lane 0 4 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 4123 3456 1164 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_rx_5lane 0 5 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 5028 4218 1388 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_rx_6lane 0 6 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 6010 4979 1637 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_rx_7lane 0 7 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 6946 5740 1846 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_rx_8lane 0 8 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 7821 6501 2067 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_1lane 1 1 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1289 912 468 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_2lane 1 2 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1522 1179 552 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_3lane 1 3 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1768 1430 658 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_4lane 1 4 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2016 1681 761 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_5lane 1 5 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2278 1932 850 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_6lane 1 6 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2534 2183 959 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_7lane 1 7 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2795 2434 1058 0 0 0 0 PRODUCTION 1.19 2017-08-11
xc7a200t ffg1156 -2 GTPE2_tx_8lane 1 8 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 3035 2685 1167 0 0 0 0 PRODUCTION 1.19 2017-08-11

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTXE2_CHANNEL BUFG Speedfile Status
xc7k325t ffg900 -2 GTXE2_rx_1lane 0 1 1024 0 0 100 rx_core_clk=156 s_axi_aclk=100 1453 1193 494 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 2264 1955 729 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 3241 2717 946 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 4140 3478 1170 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 5031 4240 1399 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 6026 5001 1631 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 6952 5762 1857 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 7833 6523 2070 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_1lane 1 1 1 false false false 0 0 100 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/RXOUTCLK=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/RXOUTCLKFABRIC=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/TXOUTCLK=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/TXOUTCLKFABRIC=156 refclk_p=156 s_axi_aclk=100 1522 1267 592 0 0 0 1 1 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1527 1201 564 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1775 1452 671 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2027 1703 762 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2294 1954 858 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2542 2205 967 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2800 2456 1074 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 3059 2707 1157 0 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTHE3_CHANNEL Speedfile Status
xcku040 ffva1156 -2 GTHE3_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1403 1171 492 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 2220 1933 765 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 3188 2695 1018 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4041 3456 1252 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4917 4218 1523 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5837 4979 1790 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 6717 5740 2063 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 7631 6501 2353 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_1lane 1 1 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1301 921 436 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1533 1172 536 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1750 1423 624 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1984 1674 718 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2229 1925 798 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2468 2176 890 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2709 2427 994 0 0 0 0 PRODUCTION 1.23 03-22-2017
xcku040 ffva1156 -2 GTHE3_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2930 2678 1093 0 0 0 0 PRODUCTION 1.23 03-22-2017

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTHE2_CHANNEL Speedfile Status
xc7vx690t ffg1761 -2 GTHE2_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1443 1171 485 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 2250 1933 720 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 3245 2695 943 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4123 3456 1163 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5028 4218 1391 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 6025 4979 1621 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 6945 5740 1848 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 7829 6501 2068 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_1lane 1 1 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1284 912 467 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1522 1179 561 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1765 1430 656 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2016 1681 765 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2281 1932 841 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2536 2183 955 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2796 2434 1042 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 3031 2685 1147 0 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTYE4_CHANNEL Speedfile Status
xcvu3p ffvc1517 -2 GTYE4_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1403 1171 491 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_rx_2lane 0 2 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 2221 1933 745 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_rx_3lane 0 3 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 3189 2695 1004 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_rx_4lane 0 4 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4043 3456 1261 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_rx_5lane 0 5 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4912 4218 1488 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_rx_6lane 0 6 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 5833 4979 1753 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_rx_7lane 0 7 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 6715 5740 1992 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_rx_8lane 0 8 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 7636 6501 2266 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_1lane 1 1 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1305 921 437 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_2lane 1 2 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1533 1172 523 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_3lane 1 3 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1750 1423 624 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_4lane 1 4 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1982 1674 701 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_5lane 1 5 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2226 1925 794 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_6lane 1 6 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2468 2176 899 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_7lane 1 7 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2707 2427 977 0 0 0 0 ADVANCED 1.04 03-29-2017
xcvu3p ffvc1517 -2 GTYE4_tx_8lane 1 8 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2928 2678 1075 0 0 0 0 ADVANCED 1.04 03-29-2017

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs GTHE4_CHANNEL Speedfile Status
xczu9eg ffvb1156 -1 GTHE4_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1404 1171 488 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_rx_2lane 0 2 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 2223 1933 741 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_rx_3lane 0 3 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 3190 2695 1016 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_rx_4lane 0 4 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4040 3456 1230 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_rx_5lane 0 5 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4919 4218 1480 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_rx_6lane 0 6 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 5832 4979 1743 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_rx_7lane 0 7 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 6707 5740 2012 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_rx_8lane 0 8 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 7630 6501 2285 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_1lane 1 1 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1308 921 440 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_2lane 1 2 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1534 1172 523 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_3lane 1 3 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1750 1423 621 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_4lane 1 4 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1984 1674 714 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_5lane 1 5 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2229 1925 799 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_6lane 1 6 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2465 2176 885 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_7lane 1 7 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2706 2427 972 0 0 0 0 ADVANCED 1.05 04-06-2016
xczu9eg ffvb1156 -1 GTHE4_tx_8lane 1 8 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2927 2678 1073 0 0 0 0 ADVANCED 1.05 04-06-2016

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