Performance and Resource Utilization for Partial Reconfiguration Decoupler v1.0

Vivado Design Suite Release 2015.3

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
INTF.INTF_0.VLNV
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t fbg676 -1 xc7k325tfbg676-1_0 1 0 xilinx.com:signal:data_rtl:1.0 aclk 903 4 1 4 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 743 16 7 16 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_2 1 0 xilinx.com:interface:aximm_rtl:1.0 aclk 1202 8 1 8 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_3 1 0 xilinx.com:interface:axis_rtl:1.0 aclk 938 4 1 4 0 0 0 PRODUCTION 1.12 2014-09-11

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
INTF.INTF_0.VLNV
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku040 fbva676 -1 xcku040-fbva676-1-i_0 1 0 xilinx.com:signal:data_rtl:1.0 aclk 1782 4 1 4 0 0 0 PRODUCTION 1.18.02 08-21-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 915 12 7 10 0 0 0 PRODUCTION 1.18.02 08-21-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_2 1 0 xilinx.com:interface:aximm_rtl:1.0 aclk 1712 8 1 8 0 0 0 PRODUCTION 1.18.02 08-21-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_3 1 0 xilinx.com:interface:axis_rtl:1.0 aclk 1782 4 1 4 0 0 0 PRODUCTION 1.18.02 08-21-2015

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
INTF.INTF_0.VLNV
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_0 1 0 xilinx.com:signal:data_rtl:1.0 aclk 1202 4 1 4 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 735 16 7 16 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_2 1 0 xilinx.com:interface:aximm_rtl:1.0 aclk 1278 8 1 8 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_3 1 0 xilinx.com:interface:axis_rtl:1.0 aclk 1214 4 1 4 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
INTF.INTF_0.VLNV
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_0 1 0 xilinx.com:signal:data_rtl:1.0 aclk 1771 4 1 4 0 0 0 ADVANCED 1.17.02 08-21-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 923 12 7 11 0 0 0 ADVANCED 1.17.02 08-21-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_2 1 0 xilinx.com:interface:aximm_rtl:1.0 aclk 1741 8 1 8 0 0 0 ADVANCED 1.17.02 08-21-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_3 1 0 xilinx.com:interface:axis_rtl:1.0 aclk 1771 4 1 4 0 0 0 ADVANCED 1.17.02 08-21-2015

Zynq-7000

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
INTF.INTF_0.VLNV
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7z045 fbg676 -1 xc7z045fbg676-1_0 1 0 xilinx.com:signal:data_rtl:1.0 aclk 1208 4 1 4 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 649 16 7 15 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_2 1 0 xilinx.com:interface:aximm_rtl:1.0 aclk 1178 8 1 8 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_3 1 0 xilinx.com:interface:axis_rtl:1.0 aclk 1219 4 1 4 0 0 0 PRODUCTION 1.11 2014-09-11

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