Performance and Resource Utilization for Partial Reconfiguration Controller v1.0

Vivado Design Suite Release 2015.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The testcases vary the number of Virtual Socket Managers and Reconfigurable Modules per Virtual Socket Manager. These values are encoded into the configuration name.

All Virtual Socket Managers and Reconfigurable Modules in a testcase are configured identically.

All testcases have the following global configuration options:

All Virtual Socket Managers have the following configuration options:

All Reconfigurable Modules have the following configuration options:

Any configuration parameters that are not listed have their default values. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm01_rm002 icap_clk=100 clk 320 1171 1203 1458 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm01_rm064 icap_clk=100 clk 309 1478 1548 1788 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm02_rm002 icap_clk=100 clk 370 1624 1571 1976 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm02_rm064 icap_clk=100 clk 314 2186 2253 2687 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm04_rm002 icap_clk=100 clk 343 2388 2179 2915 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm04_rm064 icap_clk=100 clk 320 3632 3535 4412 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm32_rm002 icap_clk=100 clk 337 15479 18256 18857 0 0 0 PRODUCTION 1.12 2014-09-11
xc7k325t fbg676 -1 xc7k325tfbg676-1_vsm32_rm064 icap_clk=100 clk 331 25564 30168 30265 0 0 0 PRODUCTION 1.12 2014-09-11

Kintex UltraScale FPGAs

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm01_rm002 icap_clk=100 clk 370 1093 1193 1331 0 0 0 PRODUCTION 1.14.6 02-25-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm01_rm064 icap_clk=100 clk 292 1343 1533 1618 0 0 0 PRODUCTION 1.14.6 02-25-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm02_rm002 icap_clk=100 clk 410 1480 1553 1765 0 0 0 PRODUCTION 1.14.6 02-25-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm02_rm064 icap_clk=100 clk 393 2015 2225 2333 0 0 0 PRODUCTION 1.14.6 02-25-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm04_rm002 icap_clk=100 clk 404 2140 2145 2480 0 0 0 PRODUCTION 1.14.6 02-25-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm04_rm064 icap_clk=100 clk 370 3226 3481 3661 0 0 0 PRODUCTION 1.14.6 02-25-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm32_rm002 icap_clk=100 clk 388 13593 17705 16023 0 0 0 PRODUCTION 1.14.6 02-25-2015
xcku040 fbva676 -1 xcku040-fbva676-1-i_vsm32_rm064 icap_clk=100 clk 376 22229 29137 25500 0 0 0 PRODUCTION 1.14.6 02-25-2015

Virtex7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm01_rm002 icap_clk=100 clk 320 1170 1203 1481 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm01_rm064 icap_clk=100 clk 298 1476 1548 1836 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm02_rm002 icap_clk=100 clk 370 1625 1571 1993 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm02_rm064 icap_clk=100 clk 286 2152 2253 2687 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm04_rm002 icap_clk=100 clk 348 2393 2179 2866 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm04_rm064 icap_clk=100 clk 314 3610 3535 4328 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm32_rm002 icap_clk=100 clk 331 15472 18256 18598 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 xc7vx690tffg1157-1_vsm32_rm064 icap_clk=100 clk 325 25580 30168 30490 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale FPGAs

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm01_rm002 icap_clk=100 clk 343 1089 1193 1352 0 0 0 ADVANCED 1.14.6 02-25-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm01_rm064 icap_clk=100 clk 325 1345 1533 1644 0 0 0 ADVANCED 1.14.6 02-25-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm02_rm002 icap_clk=100 clk 415 1475 1553 1789 0 0 0 ADVANCED 1.14.6 02-25-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm02_rm064 icap_clk=100 clk 410 2006 2225 2395 0 0 0 ADVANCED 1.14.6 02-25-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm04_rm002 icap_clk=100 clk 410 2145 2145 2622 0 0 0 ADVANCED 1.14.6 02-25-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm04_rm064 icap_clk=100 clk 382 3243 3481 3784 0 0 0 ADVANCED 1.14.6 02-25-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm32_rm002 icap_clk=100 clk 382 13527 17705 16307 0 0 0 ADVANCED 1.14.6 02-25-2015
xcvu095 ffvc1517 -1 xcvu095-ffvc1517-1-i-es2_vsm32_rm064 icap_clk=100 clk 359 22229 29137 26234 0 0 0 ADVANCED 1.14.6 02-25-2015

Zynq

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm01_rm002 icap_clk=100 clk 337 1163 1203 1443 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm01_rm064 icap_clk=100 clk 298 1478 1548 1854 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm02_rm002 icap_clk=100 clk 365 1617 1571 1949 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm02_rm064 icap_clk=100 clk 309 2163 2253 2628 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm04_rm002 icap_clk=100 clk 343 2386 2179 2938 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm04_rm064 icap_clk=100 clk 331 3612 3535 4315 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm32_rm002 icap_clk=100 clk 337 15501 18256 19255 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 fbg676 -1 xc7z045fbg676-1_vsm32_rm064 icap_clk=100 clk 337 25557 30168 30282 0 0 0 PRODUCTION 1.11 2014-09-11

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