Performance and Resource Utilization for Reed-Solomon Encoder v9.0

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 494 205 213 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 275 306 303 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 265 738 491 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 505 176 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 483 325 322 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 461 202 208 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 467 172 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 500 86 105 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 615 206 213 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 336 299 303 0 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 330 718 491 0 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 615 175 181 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 593 325 322 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 533 201 208 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 669 172 181 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 615 86 105 0 0 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 932 203 213 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 440 296 303 0 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 467 728 491 0 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 927 176 181 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 330 322 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 822 205 208 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 894 173 181 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 88 105 0 0 0 PRODUCTION 1.23 03-18-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 483 206 213 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 265 305 303 0 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 260 738 491 0 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 461 176 181 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 500 296 322 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 456 203 208 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 483 174 181 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 516 88 105 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 625 205 213 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 347 303 303 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 325 714 491 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 675 175 181 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 599 329 322 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 588 204 208 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 631 172 181 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 675 86 105 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 910 202 213 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 467 301 303 0 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 494 739 491 0 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 905 174 181 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 855 331 322 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 866 204 208 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 883 173 181 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 85 105 0 0 0 PRODUCTION 1.23 03-18-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 916 204 213 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 467 300 303 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 467 726 491 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 960 175 181 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 329 322 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 839 205 208 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 975 173 181 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 86 105 0 0 0 PRODUCTION 1.25 05-09-2019

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