Resource Utilization for Video PHY Controller v2.2

Vivado Design Suite Release 2018.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7a35t csg325 -3 char_a7_test_hdmi_phy_gtpe2_t1 148.5 GTPE2 2.97 2.97 297.000 2.97 2.97 297.000 3 HDMI 3 HDMI 1 0 6 5 4 false true true 2 DUT/inst/RX_LCLK_BUF_INST/O=125 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 gteastrefclk0_in=125 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 6236 7266 2736 3 0 0 PRODUCTION 1.22 2018-03-21
xc7a35t csg325 -3 char_a7_test_hdmi_phy_gtpe2_t13 148.5 GTPE2 2.97 2.97 297.000 2.97 2.97 297.000 3 HDMI 3 None 1 9 5 4 false true 4 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1968 4086 696 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a35t csg325 -3 char_a7_test_hdmi_phy_gtpe2_t17 148.5 GTPE2 2.97 2.97 297.000 2.97 2.97 297.000 3 HDMI 3 HDMI 1 0 5 4 false false true 2 DUT/inst/RX_LCLK_BUF_INST/O=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 2023 4441 741 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a35t csg325 -3 char_a7_test_hdmi_phy_gtpe2_t25 148.5 GTPE2 2.97 2.97 297.000 2.97 2.97 297.000 3 None 3 HDMI 1 0 5 4 false false true 2 DUT/inst/RX_LCLK_BUF_INST/O=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 1949 4081 690 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a35t csg325 -3 char_a7_test_hdmi_phy_gtpe2_t29 148.5 GTPE2 2.97 2.97 297.000 2.97 2.97 297.000 3 HDMI 3 None 1 8 5 4 false true 2 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1969 4086 691 0 0 0 PRODUCTION 1.22 2018-03-21
xc7a35t csg325 -3 char_a7_test_hdmi_phy_gtpe2_t9 148.5 GTPE2 2.97 2.97 297.000 2.97 2.97 297.000 3 None 3 HDMI 1 0 6 5 4 false true true 4 DUT/inst/RXPLL_LCLK_BUF_INST/O=125 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/RXOUTCLKFABRIC=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/U0/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtpe2_i/TXOUTCLKFABRIC=297 gteastrefclk0_in=125 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 6640 7815 3014 3 0 0 PRODUCTION 1.22 2018-03-21

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t ffg900 -2 char_k7_test_hdmi_phy_gtxe2_t1 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 HDMI 1 0 2 3 0 false true true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 gtnorthrefclk0_in=125 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 5632 6385 2497 3 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 char_k7_test_hdmi_phy_gtxe2_t13 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 None 1 5 3 0 false true 4 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=149 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1363 3263 447 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 char_k7_test_hdmi_phy_gtxe2_t17 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 HDMI 1 0 3 0 false false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1418 3535 487 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 char_k7_test_hdmi_phy_gtxe2_t25 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 None 3 HDMI 1 0 3 0 false false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 1309 3013 410 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 char_k7_test_hdmi_phy_gtxe2_t29 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 None 1 4 3 0 false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1363 3263 446 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480tl ffv1156 -2L char_k7_test_hdmi_phy_gtxe2_t9 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 None 3 HDMI 1 0 2 3 0 false true true 4 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=149 gtnorthrefclk0_in=125 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 5907 6290 2690 3 0 0 PRODUCTION 1.09 2013-11-03
xc7k480t ffv1156 -1 phy_k7_sp1_ch1_gtx_test 40.0 X0Y0 1.62 1.62 162.000 1.62 1.62 162.000 1 DP 1 DP 1 0 0 3 0 false false false DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 mgtrefclk0_pad_p_in=100 mgtrefclk1_pad_p_in=100 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1069 2046 240 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffv1156 -1 phy_k7_sp1_ch1_rx_none_gtx_test X0Y0 1.62 1.62 162.000 1.62 1.62 162.000 1 DP 4 None 1 0 0 3 0 false false false DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 mgtrefclk0_pad_p_in=100 mgtrefclk1_pad_p_in=100 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1068 2042 243 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffv1156 -1 phy_k7_sp1_ch4_gtx_test 40.0 X0Y0 1.62 1.62 162.000 1.62 1.62 162.000 1 DP 1 DP 1 0 0 3 0 false false false DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 mgtrefclk0_pad_p_in=100 mgtrefclk1_pad_p_in=100 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1069 2046 240 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffv1156 -3 phy_k7_sp3_ch4_adv_mode_gtx_test 40.0 X0Y0 1.62 1.62 162.000 1.62 1.62 162.000 4 DP 4 DP 1 0 0 3 0 true false false DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 gtnorthrefclk0_in=100 gtnorthrefclk1_in=100 gtsouthrefclk0_in=100 gtsouthrefclk1_in=100 mgtrefclk0_in=100 mgtrefclk1_in=100 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1850 3872 727 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffv1156 -3 phy_k7_sp3_ch4_buf_bypass_mode_gtx_test 40.0 X0Y0 1.62 1.62 162.000 1.62 1.62 162.000 4 DP 4 DP 1 0 0 3 0 false false true DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 mgtrefclk0_pad_p_in=100 mgtrefclk1_pad_p_in=100 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1943 4282 806 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffv1156 -3 phy_k7_sp3_tx_ch1_rx_ch2_gtx_test 40.0 X0Y0 1.62 1.62 162.000 1.62 1.62 162.000 1 DP 2 DP 1 0 0 3 0 false false false DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 mgtrefclk0_pad_p_in=100 mgtrefclk1_pad_p_in=100 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1347 2654 410 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku040 ffva1156 -2 char_ku_test_hdmi_phy_gthe3_t13 100.0 GTHE3 X0Y0 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 1 5 6 0 false true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK=149 drpclk=40 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1408 3471 482 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 char_ku_test_hdmi_phy_gthe3_t17 100.0 GTHE3 X0Y0 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK=297 drpclk=40 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1473 3827 517 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 char_ku_test_hdmi_phy_gthe3_t25 100.0 GTHE3 X0Y0 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK=297 drpclk=40 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 1363 3183 434 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 char_ku_test_hdmi_phy_gthe3_t30 100.0 GTHE3 X0Y0 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 2 5 6 0 false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK=297 drpclk=40 gtnorthrefclk00_in=297 gtnorthrefclk01_in=297 gtnorthrefclk0_in=297 gtnorthrefclk0_odiv2_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1410 3471 478 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 char_ku_test_hdmi_phy_gthe3_t9 100.0 GTHE3 X0Y0 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 2 6 0 false true true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 6003 6418 2766 3 0 0 PRODUCTION 1.24.01 01-12-2017
xcku060 ffva1156 -1 phy_gthe3_sp1_ch1_rx_none_test X0Y16 1.62 1.62 1.62 1.62 1 DP 4 None 1 0 0 0 false false false drpclk=40 mgtrefclk0_pad_p_in=162 mgtrefclk1_pad_p_in=162 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 940 2330 180 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 phy_gthe3_sp2_ch4_test 40.0 X0Y16 1.62 1.62 1.62 1.62 4 DP 4 DP 1 0 0 0 false false false drpclk=40 mgtrefclk0_pad_p_in=162 mgtrefclk1_pad_p_in=162 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1129 3997 323 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku115 flvd1924 -2 phy_gthe3_sp2_ch4_tx_none_test 40.0 X0Y16 1.62 1.62 1.62 1.62 4 None 4 DP 1 0 0 0 false false false drpclk=40 mgtrefclk0_pad_p_in=162 mgtrefclk1_pad_p_in=162 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 1126 3773 308 0 0 0 PRODUCTION 1.25.01 01-12-2017
xcku060 ffva1517 -2 phy_gthe3_sp2_tx_ch1_rx_ch2_test 40.0 X0Y16 1.62 1.62 1.62 1.62 1 DP 2 DP 1 0 0 0 false false false drpclk=40 mgtrefclk0_pad_p_in=162 mgtrefclk1_pad_p_in=162 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1038 2913 231 0 0 0 PRODUCTION 1.24.01 01-12-2017
xcku040 ffva1156 -2 phy_gthe3_txbuf_bypass_sp2_ch4_test 40.0 X0Y16 1.62 1.62 1.62 1.62 4 DP 4 DP 1 0 0 0 false false true drpclk=40 mgtrefclk0_pad_p_in=162 mgtrefclk1_pad_p_in=162 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 1162 4291 330 0 0 0 PRODUCTION 1.24.01 01-12-2017

Kintex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku9p ffve900 -3 char_kuplus_test_hdmi_phy_gthe4_t1 100.0 GTHE4 X0Y0 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 2 6 0 false true true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 7383 9006 3224 3 0 0 ADVANCE 1.20 05-21-2018
xcku9p ffve900 -3 char_kuplus_test_hdmi_phy_gthe4_t13 100.0 GTHE4 X0Y0 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 1 5 6 0 false true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3112 5828 1178 0 0 0 ADVANCE 1.20 05-21-2018
xcku9p ffve900 -3 char_kuplus_test_hdmi_phy_gthe4_t17 100.0 GTHE4 X0Y0 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3170 6184 1215 0 0 0 ADVANCE 1.20 05-21-2018
xcku9p ffve900 -3 char_kuplus_test_hdmi_phy_gthe4_t25 100.0 GTHE4 X0Y0 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 3061 5526 1128 0 0 0 ADVANCE 1.20 05-21-2018
xcku9p ffve900 -3 char_kuplus_test_hdmi_phy_gthe4_t30 100.0 GTHE4 X0Y0 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 2 5 6 0 false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk00_in=297 gtnorthrefclk01_in=297 gtnorthrefclk0_in=297 gtnorthrefclk0_odiv2_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3111 5828 1199 0 0 0 ADVANCE 1.20 05-21-2018
xcku9p ffve900 -3 char_kuplus_test_hdmi_phy_gthe4_t9 100.0 GTHE4 X0Y0 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 2 6 0 false true true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 7640 8768 3437 3 0 0 ADVANCE 1.20 05-21-2018

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7v585t ffg1157 -3 char_v7_test_hdmi_phy_gtxe2_t1 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 HDMI 1 0 2 3 0 false true true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 gtnorthrefclk0_in=125 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 5632 6385 2485 3 0 0 PRODUCTION 1.12 2014-09-11
xc7v585t ffg1157 -3 char_v7_test_hdmi_phy_gtxe2_t13 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 None 1 5 3 0 false true 4 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=149 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1363 3263 446 0 0 0 PRODUCTION 1.12 2014-09-11
xc7v585t ffg1157 -3 char_v7_test_hdmi_phy_gtxe2_t17 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 HDMI 1 0 3 0 false false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1418 3535 482 0 0 0 PRODUCTION 1.12 2014-09-11
xc7v585t ffg1157 -3 char_v7_test_hdmi_phy_gtxe2_t25 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 None 3 HDMI 1 0 3 0 false false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 1309 3013 413 0 0 0 PRODUCTION 1.12 2014-09-11
xc7v585t ffg1157 -3 char_v7_test_hdmi_phy_gtxe2_t29 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 None 1 4 3 0 false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1363 3263 446 0 0 0 PRODUCTION 1.12 2014-09-11
xc7v585t ffg1157 -3 char_v7_test_hdmi_phy_gtxe2_t9 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 None 3 HDMI 1 0 2 3 0 false true true 4 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=149 gtnorthrefclk0_in=125 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 5882 6290 2694 3 0 0 PRODUCTION 1.12 2014-09-11
xc7v585t ffg1157 -2 phy_v7_sp2_ch4_tx_none_gtx_test 40.0 GTXE2 X0Y0 1.62 1.62 162.000 1.62 1.62 162.000 4 None 4 DP 1 0 0 3 0 false false false DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt0_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt1_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt2_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/RXOUTCLKFABRIC=162 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLK=40 DUT/inst/gt_wrapper_inst/inst/my_ip_gtwrapper_i/gt3_my_ip_gtwrapper_i/gtxe2_i/TXOUTCLKFABRIC=162 mgtrefclk0_pad_p_in=100 mgtrefclk1_pad_p_in=100 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 1844 3872 718 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu190 flgc2104 -2 char_vu_test_hdmi_phy_gthe3_t1 100.0 GTHE3 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 2 6 0 false true true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK=297 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 5743 6649 2567 3 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu190 flgc2104 -2 char_vu_test_hdmi_phy_gthe3_t13 100.0 GTHE3 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 1 5 6 0 false true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK=149 drpclk=40 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1411 3471 480 0 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu190 flgc2104 -2 char_vu_test_hdmi_phy_gthe3_t25 100.0 GTHE3 X0Y4 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK=297 drpclk=40 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 1361 3183 438 0 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu190 flgc2104 -2 char_vu_test_hdmi_phy_gthe3_t30 100.0 GTHE3 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 2 5 6 0 false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK=297 drpclk=40 gtnorthrefclk00_in=297 gtnorthrefclk01_in=297 gtnorthrefclk0_in=297 gtnorthrefclk0_odiv2_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1410 3471 481 0 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu190 flgc2104 -2 char_vu_test_hdmi_phy_gthe3_t9 100.0 GTHE3 X0Y4 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 2 6 0 false true true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.my_ip_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[1].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 6005 6418 2722 3 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu080 ffvd1517 -2 phy_gthe3_sp2_ch1_adv_mode_test 40.0 X0Y16 1.62 1.62 1.62 1.62 1 DP 1 DP 1 0 0 0 true false false drpclk=100 gtnorthrefclk00_in=162 gtnorthrefclk01_in=162 gtnorthrefclk10_in=162 gtnorthrefclk11_in=162 gtsouthrefclk00_in=162 gtsouthrefclk01_in=162 gtsouthrefclk10_in=162 gtsouthrefclk11_in=162 mgtrefclk0_in=162 mgtrefclk1_in=162 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=135 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=135 966 2373 175 0 0 0 PRODUCTION 1.25.01 01-12-2017

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flga2104 -2L char_vuplus_test_hdmi_phy_gtye4_t1 100.0 GTYE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 2 6 0 false true true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 7383 9006 3238 3 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flga2104 -2L char_vuplus_test_hdmi_phy_gtye4_t13 100.0 GTYE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 1 5 6 0 false true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3093 5828 1173 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flga2104 -2L char_vuplus_test_hdmi_phy_gtye4_t17 100.0 GTYE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3154 6184 1215 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flga2104 -2L char_vuplus_test_hdmi_phy_gtye4_t25 100.0 GTYE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 3044 5526 1143 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flga2104 -2L char_vuplus_test_hdmi_phy_gtye4_t30 100.0 GTYE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 2 5 6 0 false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk00_in=297 gtnorthrefclk01_in=297 gtnorthrefclk0_in=297 gtnorthrefclk0_odiv2_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3094 5828 1178 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flga2104 -2L char_vuplus_test_hdmi_phy_gtye4_t9 100.0 GTYE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 2 6 0 false true true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gtye4_top.my_ip_gtwrapper_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 7638 8768 3450 3 0 0 PRODUCTION 1.20 05-21-2018

Zynq-7000

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7z030 fbg484 -3 char_zynq_test_hdmi_phy_gtxe2_t1 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 HDMI 1 0 2 3 0 false true true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 gtnorthrefclk0_in=125 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 5632 6385 2472 3 0 0 PRODUCTION 1.11 2014-09-11
xc7z030 fbg484 -3 char_zynq_test_hdmi_phy_gtxe2_t13 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 None 1 5 3 0 false true 4 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=149 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1363 3263 448 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z030 fbg484 -3 char_zynq_test_hdmi_phy_gtxe2_t17 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 HDMI 1 0 3 0 false false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1418 3535 483 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z030 fbg484 -3 char_zynq_test_hdmi_phy_gtxe2_t25 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 None 3 HDMI 1 0 3 0 false false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=297 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 1309 3013 415 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z030 fbg484 -3 char_zynq_test_hdmi_phy_gtxe2_t29 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 HDMI 3 None 1 4 3 0 false true 2 DUT/inst/XCVR_CH0_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/TXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/TXOUTCLK=297 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 1363 3263 448 0 0 0 PRODUCTION 1.11 2014-09-11
xc7z030 fbg484 -3 char_zynq_test_hdmi_phy_gtxe2_t9 100.0 GTXE2 5.94 5.94 148.500 5.94 5.94 148.500 3 None 3 HDMI 1 0 2 3 0 false true true 4 DUT/inst/XCVR_CH0_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH1_INST/gtxe2_i/RXOUTCLK DUT/inst/XCVR_CH2_INST/gtxe2_i/RXOUTCLK=149 gtnorthrefclk0_in=125 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 5882 6290 2687 3 0 0 PRODUCTION 1.11 2014-09-11

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
DRPCLK_FREQ
Transceiver
CHANNEL_SITE
Tx_GT_Line_Rate
Tx_Max_GT_Line_Rate
Tx_GT_Ref_Clock_Freq
Rx_GT_Line_Rate
Rx_Max_GT_Line_Rate
Rx_GT_Ref_Clock_Freq
C_Tx_No_Of_Channels
C_Tx_Protocol
C_Rx_No_Of_Channels
C_Rx_Protocol
C_TX_REFCLK_SEL
C_RX_REFCLK_SEL
C_NIDRU_REFCLK_SEL
C_TX_PLL_SELECTION
C_RX_PLL_SELECTION
Adv_Clk_Mode
C_NIDRU
Tx_Buffer_Bypass
C_INPUT_PIXELS_PER_CLOCK
C_VIPER_REG
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 char_zynqplus_test_hdmi_phy_gthe4_t1 100.0 GTHE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 2 6 0 false true true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 7380 9006 3208 3 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 char_zynqplus_test_hdmi_phy_gthe4_t13 100.0 GTHE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 1 5 6 0 false true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk1_pad_p_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3107 5828 1208 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 char_zynqplus_test_hdmi_phy_gthe4_t17 100.0 GTHE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk0_pad_p_in=297 mgtrefclk1_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3173 6184 1235 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 char_zynqplus_test_hdmi_phy_gthe4_t25 100.0 GTHE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 6 0 false false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 3058 5526 1122 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 char_zynqplus_test_hdmi_phy_gthe4_t30 100.0 GTHE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 HDMI 3 None 2 5 6 0 false true 2 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK=297 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk00_in=297 gtnorthrefclk01_in=297 gtnorthrefclk0_in=297 gtnorthrefclk0_odiv2_in=297 tx_tmds_clk=297 tx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_sb_aclk=100 vid_phy_tx_axi4s_aclk=149 3112 5828 1183 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 char_zynqplus_test_hdmi_phy_gthe4_t9 100.0 GTHE4 X0Y4 5.94 5.94 297 5.94 5.94 297 3 None 3 HDMI 1 0 2 6 0 false true true 4 true DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst/O=149 DUT/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.my_ip_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=149 drpclk=40 gtnorthrefclk0_in=156 gtnorthrefclk0_odiv2_in=156 mgtrefclk0_pad_p_in=297 rx_tmds_clk=297 rx_video_clk=149 vid_phy_axi4lite_aclk=100 vid_phy_rx_axi4s_aclk=149 vid_phy_sb_aclk=100 7679 8768 3426 3 0 0 PRODUCTION 1.20 05-21-2018

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