Resource Utilization for DMA/Bridge Subsystem for PCI Express (PCIe) v4.1

Vivado Design Suite Release 2018.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_rnum_rids
xdma_wnum_rids
xdma_axi_intf_mm
en_axi_slave_if
en_axi_master_if
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1761 -3 fcsvrg1x8_chnl1_64bit X1 8.0_GT/s 64_bit 1 1 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=125 sys_clk=100 11567 12360 5705 0 14 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -3 fcsvrg1x8_chnl4_64bit X1 8.0_GT/s 64_bit 4 4 64 32 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=125 sys_clk=100 28193 28880 13172 0 26 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -3 fcsvrg2x8_chnl1_128bit X8 5.0_GT/s 128_bit 1 1 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=250 sys_clk=100 17369 17222 8229 0 25 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -3 fcsvrg3x8_chnl1_256bit X8 8.0_GT/s 256_bit 1 1 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=250 sys_clk=100 24064 21039 10211 0 33 12 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_rnum_rids
xdma_wnum_rids
xdma_axi_intf_mm
en_axi_slave_if
en_axi_master_if
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 -3 xcvu095g1x1_chnl1_mm X1 2.5_GT/s 1 1 AXI_Memory_Mapped axi_aclk=62 sys_clk=100 sys_clk_gt=100 11059 12167 5246 0 14 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -3 xcvu095g1x1_chnl1_stream X1 2.5_GT/s 1 1 AXI_Stream axi_aclk=62 sys_clk=100 sys_clk_gt=100 10095 10822 4691 0 15 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -3 xcvu095g1x1_chnl4_mm X1 2.5_GT/s 4 4 AXI_Memory_Mapped axi_aclk=62 sys_clk=100 sys_clk_gt=100 26153 27231 11657 0 26 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -3 xcvu095g1x1_chnl4_stream X1 2.5_GT/s 4 4 AXI_Stream axi_aclk=62 sys_clk=100 sys_clk_gt=100 25700 25215 11000 0 30 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl1_mm X8 8.0_GT/s 1 1 AXI_Memory_Mapped axi_aclk=250 sys_clk=100 sys_clk_gt=100 21327 20026 8763 0 33 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl1_stream X8 8.0_GT/s 1 1 AXI_Stream axi_aclk=250 sys_clk=100 sys_clk_gt=100 19115 18691 7843 0 34 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl4_mm X8 8.0_GT/s 4 4 AXI_Memory_Mapped axi_aclk=250 sys_clk=100 sys_clk_gt=100 36978 35137 15378 0 63 12 PRODUCTION 1.25.01 01-12-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl4_stream X8 8.0_GT/s 4 4 AXI_Stream axi_aclk=250 sys_clk=100 sys_clk_gt=100 40647 36936 15453 0 67 12 PRODUCTION 1.25.01 01-12-2017

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_rnum_rids
xdma_wnum_rids
xdma_axi_intf_mm
en_axi_slave_if
en_axi_master_if
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_16_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true true true 16 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 45408 45229 17221 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_16_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true true true 16 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 47549 47859 18425 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_32_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true true true 32 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 45912 46346 17765 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_32_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true true true 32 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 48809 48942 18985 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 44703 44576 16968 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46749 47169 18415 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 44703 44576 16968 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46749 47169 18415 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 44703 44576 16968 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46749 47169 18415 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl1_mm X16 8.0_GT/s 512_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 57487 53995 21746 0 78 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl1_stream X16 8.0_GT/s 512_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 54078 52712 20042 0 79 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl2_mm X16 8.0_GT/s 512_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 62798 59013 24182 0 96 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl2_stream X16 8.0_GT/s 512_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 63537 60470 23634 0 98 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl4_mm X16 8.0_GT/s 512_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 73936 69162 28732 0 132 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl4_stream X16 8.0_GT/s 512_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 83400 76025 29649 0 136 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl1_mm X1 2.5_GT/s 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11998 14842 5862 0 33 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl1_stream X1 2.5_GT/s 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10938 13502 5260 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl4_mm X1 2.5_GT/s 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 27013 29887 12210 0 45 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl4_stream X1 2.5_GT/s 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 26608 27874 11672 0 49 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 2.5_GT/s DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 7087 9663 3178 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 2.5_GT/s DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 7985 11480 3528 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7091 9777 3161 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 8025 11598 3516 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7091 9777 3161 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 8025 11598 3516 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl1_mm X1 8.0_GT/s 64_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 11999 14959 5797 0 33 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl1_stream X1 8.0_GT/s 64_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 10984 13622 5232 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl2_mm X1 8.0_GT/s 64_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 16964 19956 7983 0 37 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl2_stream X1 8.0_GT/s 64_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 15948 18421 7276 0 39 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl4_mm X1 8.0_GT/s 64_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 27052 30004 12200 0 45 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl4_stream X1 8.0_GT/s 64_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 26531 27990 11563 0 49 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_ep_S_8_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7091 9777 3161 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_rp_S_8_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 8025 11598 3516 0 29 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10155 13467 4674 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11386 15389 5126 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10155 13467 4674 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11386 15389 5126 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10155 13467 4674 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11386 15389 5126 0 34 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl1_mm X4 8.0_GT/s 128_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 15986 19207 7572 0 40 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl1_stream X4 8.0_GT/s 128_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 14633 17868 6805 0 41 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl2_mm X4 8.0_GT/s 128_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 20855 24172 9828 0 46 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl2_stream X4 8.0_GT/s 128_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 20095 23084 9089 0 48 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl4_mm X4 8.0_GT/s 128_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 30886 34264 13914 0 58 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl4_stream X4 8.0_GT/s 128_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 31934 33520 13670 0 62 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16791 19605 7060 0 44 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 18294 21660 7675 0 44 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16791 19605 7060 0 44 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 18294 21660 7675 0 44 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16791 19605 7060 0 44 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 18294 21660 7675 0 44 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl1_mm X8 8.0_GT/s 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 24995 26392 10501 0 52 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl1_stream X8 8.0_GT/s 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 22801 25057 9304 0 53 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl2_mm X8 8.0_GT/s 256_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 29826 31391 12985 0 62 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl2_stream X8 8.0_GT/s 256_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 29423 31127 12172 0 64 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl4_mm X8 8.0_GT/s 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 40697 41498 17015 0 82 0 PRODUCTION 1.19 03-17-2018
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl4_stream X8 8.0_GT/s 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 44442 43297 16780 0 86 0 PRODUCTION 1.19 03-17-2018

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