Discontinued IP

This user guide provides information about the Virtex®-5 LogiCORE™ Endpoint block for PCI Express® (PCIe) designs. The core instantiates the integrated Endpoint block for PCIe designs found in Virtex-5 LXT, SXT, and FXT devices.

This is the data sheet for Virtex®-5 LogiCORE Endpoint Block for PCI Express®.

The LogiCORE™ IP Fibre Channel Arbitrated Loop (FC-AL) core provides a flexible, fully verified solution for use in any FC-AL port design.

The Fibre Channel Arbitrated Loop Getting Started Guide provides information using the LogiCORE ™IP Fibre Channel Arbitrated Loop core also serves as the reference document for the example design provided with the core.

To communicate that Xilinx is discontinuing certain Development Systems Products. This notice is an early notice to all existing customers and field sales.

This is the data sheet for the FlexRay v1.1 core.

Getting Started Guide for LogiCORE™ FlexRay™ v1.1.

The LogiCORE™ IP Generic Framing Procedure (GFP) is a fully verified protocol encapsulation/de-encapsulation engine enabling efficient transport of LAN/SAN client protocols over SONET/SDH-based networks.

The LogiCORE™ IP Generic Framing Procedure Getting Started Guide provides information about generating a Generic Framing Procedure (GFP) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Generic Framing Procedure User Guide describes the function and operation of the LogiCORE™ IP Generic Framing Procedure (GFP) core, as well as information about designing, customizing, and implementing the core.

The purpose of this notification is to communicate that Xilinx is discontinuing certain Development Systems Products.

This is the data sheet for the H.264 CABAC Core v1.0 core

This is the data sheet for the H.264 CABAC Encoder Core v1.0 core.

This is the user guide for the H.264 CABAC Encoder Core v 1.0 core.

The purpose of this notification is to communicate that Xilinx is discontinuing certain Development Systems Products.

This is the user guide for the H.264 Deblocker Core v1.0 core.

This is the data sheet for the H.264 Deblocker Core v1.0 core.

This is the data sheet for the H.264 Deblocker Core v1.0 core.

The purpose of this notification is to communicate that Xilinx is discontinuing certain Development Systems Products.

The H.264 Motion Estimation Engine Version 1.0 is a fully functional netlist implemented on Xilinx® FPGAs.

The H.264 Motion Estimation Engine Version 1.0 is a fully functional netlist implemented on Xilinx® FPGAs.

The H.264 Motion Estimation Engine Version 1.0 is a fully functional netlist implemented on Xilinx® FPGAs.

This is the data sheet for the OPB Multi Channel HDLC Interface (v2.01a) core.

MPEG-4 Part 2 Simple Profile Decoder core is a fully functional VHDL design implemented on a Xilinx® FPGA. The MPEG-4 Decoder core accepts compressed video information and recreates a video image suitable for display.

The MPEG-4 Part 2 Simple Profile Decoder core is a fully functional VHDL design implemented on a Xilinx® FPGA.

This user guide describes the basic function and operation of the MPEG-4 Simple Profile Decoder core and contains information about designing, customizing, and implementing the core.

The purpose of this notification is to communicate that Xilinx is discontinuing certain Development Systems Products.

The purpose of this notification is to communicate that Xilinx is discontinuing certain Development Systems Products.

The MPEG-4 Part 2 Simple Profile Encoder core is a fully functional VHDL design implemented on a Xilinx® FPGA.

The MPEG-4 Part 2 Simple Profile Encoder core is a fully functional VHDL design implemented on a Xilinx® FPGA.

This user guide describes the MPEG-4 Simple Profile Encoder core and a suite of applications that support it.

This is the data sheet for the Packet Queue v2.2 core.

The LogiCORE™ RapidIO Physical Layer Interface is a fixed-netlist solution for the RapidIO interconnect targeting Xilinx® Virtex®-II and Virtex-II Pro FPGAs.

The LogiCORE™ IP SPI-3 Physical Layer core provides a complete, pre-engineered solution that is fully compatible with the OIF-SPI3-01.0 System Packet Interface Level-2 implementation agreement. This fully verified solution implements the SPI-3 PHY Layer interface, which interconnects with SPI-3 Link Layer devices.

The SPI-3 Physical Layer Getting Started Guide provides information about generating a LogiCORE™ IP SPI-3 Physical Layer core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

To communicate that Xilinx is discontinuing certain Development Systems products.

The LogiCORE™ IP 1-Gigabit Ethernet Media Access Controller core supports full-duplex operation at 1 Gigabit per second (Gbps), and can be used with all Gigabit Ethernet Physical Coding standards.

The 1-Gigabit Ethernet MAC Getting Started Guide provides information about generating a LogiCORE™ IP 1-Gigabit Ethernet MAC core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP 1-Gigabit Ethernet MAC User Guide provides information about generating the core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP VLYNQ™ core is a fully verified, serial, low-pin-count communications interface for cost-sensitive applications. Developed by Texas Instruments, VLYNQ enables the extension of an internal bus segment to one or more external devices in a scalable manner.

The LogiCORE™ IP VLYNQ™ core is a fully verified, serial, low-pin-count communications interface for cost-sensitive applications. Developed by Texas Instruments, VLYNQ enables the extension of an internal bus segment to one or more external devices in a scalable fashion without extensive software modification, and was originally designed as a mechanism to preserve software investment.

Product specification for Distributed Memory v7.1.

This is the data sheet for the OPB General Purpose Input/Output (GPIO) (v3.01b) core

This is the data sheet for the OPB UART Lite (v1.00b) core

This is the data sheet for the PLB to OPB Bridge (v1.01a) core

This Answer Record contains the Release Notes for the LogiCORE IP Fibre Channel v3.5 Core that was released for ISE Design Suite 12.1, and includes the following: 

• New Features 
• Resolved Issues  
• Known Issues  

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: 
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

This core has been discontinued and is to be removed in 13.1.  In order to see the core in the 12.1 Core Generator IP Catalog, the "All IP versions" box must be checked.

The LogiCORE™ IP Fibre Channel Core provides a flexible core for use in any non-loop FC port and can run at 1, 2, and 4 Gbps. The FC core includes credit management features as well as the FC (old) Port State Machine for link initialization.

The Fibre Channel Getting Started Guide provides initial information about using the LogiCORE™ IP Fibre Channel Core and provides instructions for using the example design provided with the core.

This guide describes the LogiCORE™ IP Fibre Channel core functionality and provides design and implementation guidelines.

The Xilinx LogiCORE™ IP SPI-4.2 (PL4) Lite core implements, and is functionally compliant with, the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical layer devices to link layer devices in 2.5 Gbps POS, ATM, and Ethernet applications.

This guide provides information about generating the SPI-4.2 (PL4) Lite core, customizing and simulating the core using the provided example design, and running the design files through implementation using Xilinx® tools.

This user guide describes the function and operation of the Xilinx® LogiCORE™ SPI-4.2 (PL4) Lite Core, and provides information about designing, customizing, and implementing the core.

This is the data sheet for the 802.16 LDPC Encoder v1.0 core

This is the data sheet for Synchronous FIFO 5.0.

This is a data sheet for the Asynchronous FIFO v6.1.