Processing

The Xilinx LogiCORE™ IP Color Correction Matrix core is a 3 x 3 programmable coefficient matrix multiplier with offset compensation. This core can be used for color correction operations such as adjusting white balance, color cast, brightness, and/or contrast in an RGB image.

The Color Correction Matrix provides a method for correcting the image color data. This fundamental block operates on either CMY or RGB data, and processing is “real-time” as a pre-processing hardware block. This document contains information about the AXI4 version of the core.

This document introduces the bit accurate C model for the Xilinx® LogiCORE™ IP Color Correction Matrix (CCM) v2.0 core, which has been developed primarily for system modeling.

The Xilinx LogiCORE™ IP Color Correction Matrix core is a 3 x 3 programmable coefficient matrix multiplier with offset compensation. This core can be used for color correction operations such as adjusting white balance, color cast, brightness, or contrast in an RGB image. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ Defective Pixel Correction solution is a dynamic solution that removes defective pixels from a camera image sensor array.

This user guide provides information about the Xilinx® LogiCORE™ IP Defective Pixel Correction v3.0 bit accurate C model 32-bit Windows and 64-bit Linux platforms.

The Xilinx LogiCORE™ IP Defective Pixel Correction performs real-time detection and correction of defective pixels in a camera image sensor array. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Defective Pixel Correction core performs real-time detection and correction of defective pixels in a camera image sensor array. This document contains information about the AXI4 version of the core.

To communicate that Xilinx is discontinuing certain Development Systems products relates to LogiCORE™ IP, Image Processing Pipeline and Xilinx® Development Systems Kits and Boards Products on While Supplies Last.

The Xilinx Color Filter Array Interpolation LogiCORE™ IP provides an optimized hardware block to reconstruct sub-sampled color data for images captured by a Bayer Color Filter Array image sensor. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Processing Pipeline core provides an optimized hardware block to pre-process images captured by a color image sensor fitted with a Bayer Color Filter Array (CFA). The Image Processing Pipeline core provides an efficient and lowfootprint solution to correct defective pixels, interpolate the missing color components for every pixel, correct colors to adjust to lighting conditions, and set gamma to compensate for the intensity distortion of different display devices.

The Xilinx Color Filter Array Interpolation IP LogiCORE™ provides an optimized hardware block to reconstruct sub-sampled color data for images captured by an image sensor fitted with a Bayer Color Filter Array. The color filter array overlaid over the silicon substrate enables CMOS or CCD image sensors to measure local light intensities corresponding to different wavelengths.

The Xilinx® LogiCORE™ IP Color Filter Array Interpolation (CFA) v3.0 core has a bit accurate C model designed for system modeling. A MATLAB® software pcode function for seamless MATLAB software integration is also available.

The Xilinx Color Filter Array Interpolation LogiCORE™ IP provides an optimized hardware block to reconstruct sub-sampled color data for images captured by a Bayer Color Filter Array image sensor. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Color Filter Array Interpolation core provides an optimized hardware block to reconstruct sub-sampled color data for images captured by a Bayer Color Filter Array image sensor. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Gamma Correction v3.0 has a bit accurate C model for 32-bit Windows and 64-bit Linux platforms. The model has an interface consisting of a set of C functions, which reside in a statically link library (shared library).

The Xilinx Gamma Correction LogiCORE™ provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a lookup table structure that is programmed to implement a gamma correction curve transform on the input image data.

The Xilinx Gamma Correction LogiCORE@trade; provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a look-up table structure that is programmed to implement a gamma correction curve transform on the input image data. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Gamma Correction core provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a look-up table structure that is programmed to implement a gamma correction curve transform on the input image data. This document contains information about the AXI4 version of the core.

The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. System design is made easier through support of both streaming-video and frame buffer-based interfaces. This core is designed to connect via an AXI4-Lite interface.

The LogiCORE™ IP Video Scaler v4.0 User Guide provides information about generating the Video Scaler core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The Xilinx® Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.

This user guide provides information about the Xilinx® LogiCORE™ IP Video Scaler v4.0 bit accurate C model 32-bit Windows and 64-bit Linux platforms.

The Xilinx LogiCORE™ IP Video Scaler is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. This document contains information about the AXI4 version of the core.

This guide provides information about generating the Video Scaler core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

Keywords: Design Advisory, Color Corretion Matrix, Color Filter Array Interpolation, Defective Pixel Correction, Gamma Correction, Image Processing Pipeline, On-Screen Display, Video Direct Memory Access, Video Scaler, Video Timing Controller

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This answer record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP Video Scaler Core. 

The following information is listed for each version of the core: 

• New Features 
• Bug Fixes 
• Known Issues 

The Xilinx LogiCORE™ IP Video Scaler core is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. This document contains information about the AXI4 version of the core.

The Xilinx® Video Timing Controller LogiCORE™ IP is a general purpose video timing generator and detector.

The Xilinx® Video Timing Controller LogiCORE™ IP is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.

The Xilinx Video Timing Controller LogiCORE™ IP is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Video Timing Controller core is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.

The Xilinx Video On-Screen Display LogiCORE™ IP provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

This user guide provides information about the Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) v2.0 bit accurate C model 32-bit Windows, 64-bit Windows, 32-bit Linux, and 64-bit Linux platforms.

The LogiCORE™ IP Video On-Screen Display v2.0 User Guide provides information about generating the Video On-Screen Display core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Video On-Screen Display v1.0 User Guide provides information about generating the Video On-Screen Display core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The Xilinx Video On-Screen Display LogiCORE™ IP provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation.

The Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) core provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The Xilinx® Video Direct Memory Access (Video DMA) LogiCORE™ IP allows video cores to access external memory via the Video Frame Buffer Controller (VFBC) port on the Multi-Port Memory Controller (MPMC).

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect. This document contains information about the AXI4 version of the core.

This document introduces the bit accurate C model for the Xilinx® LogiCORE™ IP Image Edge Enhancement v2.0 core, which has been developed primarily for system modeling.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect. This document contains information about the AXI4 version of the core.

This document introduces the bit accurate C model for the Xilinx® LogiCORE™ IP Image Noise Reduction v2.0 core, which has been developed primarily for system modeling.

The Xilinx Image Noise Reduction LogiCORE™ provides users with an easy to use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time.

The Xilinx LogiCORE™ IP Image Noise Reduction core is an easy-to-use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time.

The Xilinx LogiCORE™ IP Image Noise Reduction core is an easy-to-use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time. This document contains information about the AXI4 version of the core.

The Xilinx Image Statistics LogiCORE™ IP implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis.

This user guide provides information about the Xilinx® LogiCORE™ IP Images Statistics v2.0 bit accurate C model 32-bit Windows and 64-bit Linux platforms.

The Xilinx LogiCORE™ IP Image Statistics core implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Statistics core implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis. This document contains information about the AXI4 version of the core.

This user guide provides information about the Xilinx® LogiCORE™ IP Video Motion Adaptive Noise Reduction (MANR) v2.0 bit accurate C model core.

The Xilinx Motion Adaptive Noise Reduction (MANR) LogiCORE™ IP is a module for both motion detection and motion adaptive noise reduction in video systems. The core allows the motion detection function to be used independently of the noise reduction function for applications where noise reduction is not needed.

The Xilinx® LogiCORE™ IP Motion Adaptive Noise Reduction (MANR) is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.

The Xilinx Motion Adaptive Noise Reduction (MANR) LogiCORE™ IP is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Motion Adaptive Noise Reduction (MANR) is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.

The Xilinx Image Characterization LogiCORE™ IP calculates important statistical data for video input streams. The Image Characterization LogiCORE is an important processing block for many applications including face recognition and object detection.

This user guide provides information about the Xilinx® LogiCORE™ IP Image Characterization v1.1 bit accurate C model for 32-bit and 64-bit Linux platforms and 32-bit and 64-bit Windows platforms.

The Image Characterization LogiCORE™ IP is comprised of a collection of blocks that work together to calculate statistical data that can be used to describe an image in the analytics domain. This document contains information about the AXI4 version of the core.

This user guide provides information about the Xilinx® LogiCORE™ IP Image Characterization v1.1 bit accurate C model for 32-bit and 64-bit Linux platforms and 32-bit and 64-bit Windows platforms.

The Xilinx LogiCORE™ IP Color Correction Matrix core is a 3 x 3 programmable coefficient matrix multiplier with offset compensation. This core can be used for color correction operations such as adjusting white balance, color cast, brightness, and/or contrast in an RGB image.

The Xilinx Color Filter Array Interpolation IP LogiCORE™ provides an optimized hardware block to reconstruct sub-sampled color data for images captured by an image sensor fitted with a Bayer Color Filter Array. The color filter array overlaid over the silicon substrate enables CMOS or CCD image sensors to measure local light intensities corresponding to different wavelengths.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect.

The Xilinx Gamma Correction LogiCORE™ provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a lookup table structure that is programmed to implement a gamma correction curve transform on the input image data.

The Xilinx Image Noise Reduction LogiCORE™ provides users with an easy to use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time.

The Xilinx LogiCORE™ Defective Pixel Correction solution is a dynamic solution that removes defective pixels from a camera image sensor array.

The Xilinx Image Statistics LogiCORE™ IP implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis.

To communicate that Xilinx is discontinuing certain Development Systems products.

The Xilinx® LogiCORE™ IP Gamma Correction v3.0 has a bit accurate C model for 32-bit Windows and 64-bit Linux platforms. The model has an interface consisting of a set of C functions, which reside in a statically link library (shared library).

The Color Correction Matrix provides a method for correcting the image color data. This fundamental block operates on either CMY or RGB data, and processing is “real-time” as a pre-processing hardware block. This document contains information about the AXI4 version of the core.

The Xilinx Gamma Correction LogiCORE@trade; provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a look-up table structure that is programmed to implement a gamma correction curve transform on the input image data. This document contains information about the AXI4 version of the core.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Statistics core implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Defective Pixel Correction performs real-time detection and correction of defective pixels in a camera image sensor array. This document contains information about the AXI4 version of the core.

The Image Characterization LogiCORE™ IP is comprised of a collection of blocks that work together to calculate statistical data that can be used to describe an image in the analytics domain. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Noise Reduction core is an easy-to-use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time.

The Xilinx LogiCORE™ IP Image Noise Reduction core is an easy-to-use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Statistics core implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Color Filter Array Interpolation core provides an optimized hardware block to reconstruct sub-sampled color data for images captured by a Bayer Color Filter Array image sensor. This document contains information about the AXI4 version of the core.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Gamma Correction core provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a look-up table structure that is programmed to implement a gamma correction curve transform on the input image data. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Color Correction Matrix core is a 3 x 3 programmable coefficient matrix multiplier with offset compensation. This core can be used for color correction operations such as adjusting white balance, color cast, brightness, or contrast in an RGB image. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Defective Pixel Correction core performs real-time detection and correction of defective pixels in a camera image sensor array. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Object Segmentation core provides a hardware-accelerated method for identifying objects of interest within a video stream. This document contains information about the AXI4 version of the core.

The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. System design is made easier through support of both streaming-video and frame buffer-based interfaces. This core is designed to connect via an AXI4-Lite interface.

The Xilinx Image Characterization LogiCORE™ IP calculates important statistical data for video input streams. The Image Characterization LogiCORE is an important processing block for many applications including face recognition and object detection.

The LogiCORE™ IP Video Scaler v4.0 User Guide provides information about generating the Video Scaler core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The Xilinx® Video Direct Memory Access (Video DMA) LogiCORE™ IP allows video cores to access external memory via the Video Frame Buffer Controller (VFBC) port on the Multi-Port Memory Controller (MPMC).

The Xilinx® Video Timing Controller LogiCORE™ IP is a general purpose video timing generator and detector.

The Xilinx® Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.

The Xilinx Video On-Screen Display LogiCORE™ IP provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The Xilinx Motion Adaptive Noise Reduction (MANR) LogiCORE™ IP is a module for both motion detection and motion adaptive noise reduction in video systems. The core allows the motion detection function to be used independently of the noise reduction function for applications where noise reduction is not needed.

This user guide provides information about the Xilinx® LogiCORE™ IP Video Scaler v4.0 bit accurate C model 32-bit Windows and 64-bit Linux platforms.

The LogiCORE™ IP Video On-Screen Display v2.0 User Guide provides information about generating the Video On-Screen Display core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

To communicate that Xilinx is discontinuing certain Development Systems products.

This user guide provides information about the Xilinx® LogiCORE™ IP Video Motion Adaptive Noise Reduction (MANR) v2.0 bit accurate C model core.

This user guide provides information about the Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) v2.0 bit accurate C model 32-bit Windows, 64-bit Windows, 32-bit Linux, and 64-bit Linux platforms.

The LogiCORE™ IP Video On-Screen Display v1.0 User Guide provides information about generating the Video On-Screen Display core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The Xilinx Video On-Screen Display LogiCORE™ IP provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation.

This guide provides information about generating the Video Scaler core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

The Xilinx® LogiCORE™ Intellectual Property (IP) Object Segmentation core provides a hardware-accelerated method for identifying objects of interest within a video stream. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Motion Adaptive Noise Reduction (MANR) is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.

The Xilinx Video Timing Controller LogiCORE™ IP is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Video Scaler is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The Xilinx Video Deinterlacer LogiCORE™ IP provides a flexible video processing block for deinterlacing video into a progressive video structure. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Motion Adaptive Noise Reduction (MANR) is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) core provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The Xilinx Video Deinterlacer LogiCORE™ IP provides a flexible video processing block for deinterlacing video into a progressive video structure. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Video Scaler core is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Video Timing Controller core is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

This application note details bridging an XSVI interface to an AXI4-Stream interface, enabling video designs with Xilinx video IP cores and XSVI interfaces to use the AXI VDMA.

Design File(s):

• xapp521.zip

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the LogiCORE IP AXI VDMA Core.

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

This application note covers the design considerations of a video system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp741.zip

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

This application note demonstrates the creation of video systems by using Xilinx native video IP cores such as AXI Video Direct Memory Access (VDMA), Video Timing Controller (VTC), test pattern generator (TPG), and the DDR3 memory controller to process configurable frame rates and resolutions in Kintex™-7 FPGAs.

Design File(s):

• xapp742.zip

The Xilinx® LogiCORE™ IP Object Segmentation core provides a hardware-accelerated method for identifying objects of interest within a video stream. This document contains information about the AXI4 version of the core.

This user guide provides information about the Xilinx® LogiCORE™ IP Object Segmentation v1.0 bit accurate C model for 32-bit Linux, 64-bit Linux, 32-bit Windows, and 64-bit Windows platforms.

The Xilinx® LogiCORE™ Intellectual Property (IP) Object Segmentation core provides a hardware-accelerated method for identifying objects of interest within a video stream. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Virtex®-6 FPGA Triple-Rate SDI core implements triple-rate SDI receivers and transmitters. It supports SD-SDI, HD-SDI, 3G-SDI (level A, level B-DL, and level B-DS), and dual-link HD-SDI standards. The Triple-Rate SDI core is compatible with the GTX transceivers in Virtex-6 devices.

The LogiCORE™ IP Virtex®-6 FPGA Triple-Rate SDI core implements triple-rate SDI receivers and transmitters. It supports SD-SDI, HD-SDI, 3G-SDI (level A, level B-DL, and level B-DS), and dual-link HD-SDI standards. This Triple-Rate SDI core is compatible with the GTX transceivers in Virtex-6 devices.

The Xilinx Video Deinterlacer LogiCORE™ IP provides a flexible video processing block for deinterlacing video into a progressive video structure. This document contains information about the AXI4 version of the core.

The Xilinx Video Deinterlacer LogiCORE™ IP provides a flexible video processing block for deinterlacing video into a progressive video structure. This document contains information about the AXI4 version of the core.

This user guide provides information about the Xilinx® LogiCORE™ IP Image Characterization v1.1 bit accurate C model for 32-bit and 64-bit Linux platforms and 32-bit and 64-bit Windows platforms.

The Xilinx LogiCORE™ IP Color Correction Matrix core is a 3 x 3 programmable coefficient matrix multiplier with offset compensation. This core can be used for color correction operations such as adjusting white balance, color cast, brightness, and/or contrast in an RGB image.

The Xilinx® Video Timing Controller LogiCORE™ IP is a general purpose video timing generator and detector.

The Xilinx Color Filter Array Interpolation IP LogiCORE™ provides an optimized hardware block to reconstruct sub-sampled color data for images captured by an image sensor fitted with a Bayer Color Filter Array. The color filter array overlaid over the silicon substrate enables CMOS or CCD image sensors to measure local light intensities corresponding to different wavelengths.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect.

The Xilinx Gamma Correction LogiCORE™ provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a lookup table structure that is programmed to implement a gamma correction curve transform on the input image data.

The Xilinx Image Noise Reduction LogiCORE™ provides users with an easy to use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time.

The Xilinx LogiCORE™ Defective Pixel Correction solution is a dynamic solution that removes defective pixels from a camera image sensor array.

The Xilinx Image Statistics LogiCORE™ IP implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis.

The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. System design is made easier through support of both streaming-video and frame buffer-based interfaces. This core is designed to connect via an AXI4-Lite interface.

The Xilinx Motion Adaptive Noise Reduction (MANR) LogiCORE™ IP is a module for both motion detection and motion adaptive noise reduction in video systems. The core allows the motion detection function to be used independently of the noise reduction function for applications where noise reduction is not needed.

The LogiCORE™ IP Video Scaler v4.0 User Guide provides information about generating the Video Scaler core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The Xilinx® Video Direct Memory Access (Video DMA) LogiCORE™ IP allows video cores to access external memory via the Video Frame Buffer Controller (VFBC) port on the Multi-Port Memory Controller (MPMC).

The Xilinx® LogiCORE™ IP Object Segmentation core provides a hardware-accelerated method for identifying objects of interest within a video stream. This document contains information about the AXI4 version of the core.

The Xilinx® Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.

The Xilinx Video On-Screen Display LogiCORE™ IP provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The Xilinx Image Characterization LogiCORE™ IP calculates important statistical data for video input streams. The Image Characterization LogiCORE is an important processing block for many applications including face recognition and object detection.

The LogiCORE™ IP Video On-Screen Display v2.0 User Guide provides information about generating the Video On-Screen Display core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

This user guide provides information about the Xilinx® LogiCORE™ IP Video Scaler v4.0 bit accurate C model 32-bit Windows and 64-bit Linux platforms.

The Xilinx® LogiCORE™ IP Gamma Correction v3.0 has a bit accurate C model for 32-bit Windows and 64-bit Linux platforms. The model has an interface consisting of a set of C functions, which reside in a statically link library (shared library).

This user guide provides information about the Xilinx® LogiCORE™ IP Video Motion Adaptive Noise Reduction (MANR) v2.0 bit accurate C model core.

This user guide provides information about the Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) v2.0 bit accurate C model 32-bit Windows, 64-bit Windows, 32-bit Linux, and 64-bit Linux platforms.

The LogiCORE™ IP Video On-Screen Display v1.0 User Guide provides information about generating the Video On-Screen Display core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The Xilinx Video On-Screen Display LogiCORE™ IP provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation.

This guide provides information about generating the Video Scaler core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

The Xilinx® LogiCORE™ Intellectual Property (IP) Object Segmentation core provides a hardware-accelerated method for identifying objects of interest within a video stream. This document contains information about the AXI4 version of the core.

The Color Correction Matrix provides a method for correcting the image color data. This fundamental block operates on either CMY or RGB data, and processing is “real-time” as a pre-processing hardware block. This document contains information about the AXI4 version of the core.

The Xilinx Gamma Correction LogiCORE@trade; provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a look-up table structure that is programmed to implement a gamma correction curve transform on the input image data. This document contains information about the AXI4 version of the core.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Motion Adaptive Noise Reduction (MANR) is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Statistics core implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis. This document contains information about the AXI4 version of the core.

The Xilinx Video Timing Controller LogiCORE™ IP is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.

The Xilinx Color Filter Array Interpolation LogiCORE™ IP provides an optimized hardware block to reconstruct sub-sampled color data for images captured by a Bayer Color Filter Array image sensor. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Defective Pixel Correction performs real-time detection and correction of defective pixels in a camera image sensor array. This document contains information about the AXI4 version of the core.

The Image Characterization LogiCORE™ IP is comprised of a collection of blocks that work together to calculate statistical data that can be used to describe an image in the analytics domain. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Video Scaler is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The Xilinx Video Deinterlacer LogiCORE™ IP provides a flexible video processing block for deinterlacing video into a progressive video structure. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Noise Reduction core is an easy-to-use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Motion Adaptive Noise Reduction (MANR) is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Noise Reduction core is an easy-to-use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Image Statistics core implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Color Filter Array Interpolation core provides an optimized hardware block to reconstruct sub-sampled color data for images captured by a Bayer Color Filter Array image sensor. This document contains information about the AXI4 version of the core.

The Xilinx Image Edge Enhancement LogiCORE™ IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Gamma Correction core provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a look-up table structure that is programmed to implement a gamma correction curve transform on the input image data. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Video On-Screen Display (OSD) core provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. This document contains information about the AXI4 version of the core.

The Xilinx Video Deinterlacer LogiCORE™ IP provides a flexible video processing block for deinterlacing video into a progressive video structure. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Color Correction Matrix core is a 3 x 3 programmable coefficient matrix multiplier with offset compensation. This core can be used for color correction operations such as adjusting white balance, color cast, brightness, or contrast in an RGB image. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Defective Pixel Correction core performs real-time detection and correction of defective pixels in a camera image sensor array. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Video Scaler core is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP Video Timing Controller core is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Spartan®-6 FPGA Triple-Rate SDI core implements triple-rate SDI receivers and transmitters. It supports SD-SDI, HD-SDI, 3G-SDI (level A, level B-DL, and level B-DS), and dual-link HD-SDI standards. This Triple-Rate SDI core is compatible with the GTP transceivers in Spartan-6 devices.

The LogiCORE™ IP Spartan®-6 FPGA Triple-Rate SDI interface solution provides receiver and transmitter interfaces for the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards. The Spartan-6 FPGA Triple-Rate SDI receiver and transmitter are provided as unencrypted source code in both Verilog and VHDL, allowing the user to fully customize these interfaces as required by specific applications.

The Xilinx Chroma Resampler LogiCORE provides users with an easy-to-use IP block for converting between chroma sub-sampling formats. This document contains information about the AXI4 version of the core.

The Xilinx Chroma Resampler LogiCORE provides users with an easy-to-use IP block for converting between chroma sub-sampling formats. This document contains information about the AXI4 version of the core.

The Xilinx LogiCOR™ IP Video In to AXI4-Stream core is designed to interface from a video source (clocked parallel video data with synchronization signals - active video with either syncs, blanks or both) to the AXI4-Stream Video Protocol Interface. This core works in conjunction with the timing detector portion of the Xilinx Video Timing Controller (VTC) core. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP AXI4-Stream to Video Out core is designed to interface from the AXI4-Stream interface implementing a Video Protocol to a video source (parallel video data, video syncs, and blanks). The core works in conjunction with Xilinx Video Timing Controller (VTC) core, providing a bridge between video processing cores with AXI4-Stream interfaces and a video output. This document contains information about the AXI4 version of the core.