Automotive and Industrial

The MOST® NIC User Guide provides information about the LogiCORE™ IP Media Oriented System Transport (MOST) Network Interface Controller (NIC) core, including information about using, designing with, customizing, and implementing the core.

The MOST® Network Interface Controller Getting Started Guide provides information about generating a LogiCORE™ IP Media Oriented Systems Transport Network Interface Controller (MOST NIC) core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

This is the data sheet for the CAN v3.2 core.

The CAN v3.2 Getting Started Guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx FPGA families.

The LogiCORE™ IP Controller Area Network (CAN) product specification describes the architecture and features of the Xilinx CAN controller core and the functionality of the various registers in the design. In addition, the CAN core user interface and its customization options are described. This document contains information about the AXI4 version of the core.

This guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx® FPGA families.

The LogiCORE™ IP Controller Area Network (CAN) product specification describes the architecture and features of the Xilinx CAN controller core and the functionality of the various registers in the design. In addition, the CAN core user interface and its customization options are described. This document contains information about the AXI4 version of the core.

This guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

This is the data sheet for the CAN v3.2 core.

The CAN v3.2 Getting Started Guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Controller Area Network (CAN) product specification describes the architecture and features of the Xilinx CAN controller core and the functionality of the various registers in the design. In addition, the CAN core user interface and its customization options are described. This document contains information about the AXI4 version of the core.

This guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Controller Area Network (CAN) product specification describes the architecture and features of the Xilinx CAN controller core and the functionality of the various registers in the design. In addition, the CAN core user interface and its customization options are described. This document contains information about the AXI4 version of the core.

This guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The MOST NIC core is a complete controller designed to the MOST Specification revision 2.4. When combined with the Xilinx® Automotive (XA) solution and embedded processing, the MOST® NIC core lets designers leverage the MOST open standard network by providing a higher level of customization in a scalable, flexible design solution.

The MOST® NIC User Guide provides information about the LogiCORE™ IP Media Oriented System Transport (MOST) Network Interface Controller (NIC) core, including information about using, designing with, customizing, and implementing the core.

The MOST® Network Interface Controller Getting Started Guide provides information about generating a LogiCORE™ IP Media Oriented Systems Transport Network Interface Controller (MOST NIC) core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx FPGA families.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx® FPGA families.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.