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DCR Bus Structure

Date	Name
04/19/2010	Device Control Register Bus (DCR) v2.9 Data Sheet(PDF, ver 2.1, 367 KB ) This is the data sheet for the Device Control Register Bus (DCR) v2.9 core. Was this document helpful? Yes \| No

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OPB Arbiter

Date	Name
09/23/2005	OPB Arbiter (v1.02e) Data Sheet(PDF, ver 1.3, 2.22 MB ) This is the data sheet for the OPB Arbiter (v1.02e) core Was this document helpful? Yes \| No

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OPB IPIF Architecture

Date	Name
12/02/2005	OPB IPIF (v3.01c) Data Sheet(PDF, ver 1.3, 3.42 MB ) This is the data sheet for the OPB IPIF (v3.01c) core Was this document helpful? Yes \| No

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OPB to DCR Bridge

Date	Name
04/24/2009	OPB to DCR Bridge (v1.00b) Data Sheet(PDF, ver 2.0, 373 KB ) This is the data sheet for the OPB to DCR Bridge (v1.00b) core Was this document helpful? Yes \| No

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OPB to OPB Bridge (Lite Version)

Date	Name
12/02/2005	OPB to OPB Bridge (Lite Version) (v1.00a) Data Sheet(PDF, ver 1.5, 805 KB ) This is the data sheet for the OPB to OPB Bridge (Lite Version) (v1.00a) core Was this document helpful? Yes \| No

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OPB to PLB Bridge

Date	Name
04/24/2009	OPB to PLB Bridge (v1.00c) Data Sheet(PDF, ver 1.5, 1.78 MB ) This is the data sheet for the OPB to PLB Bridge (v1.00c) core. Was this document helpful? Yes \| No

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PLBv34 Bus Structure

Date	Name
02/27/2002	Processor Local Bus (PLB) Arbiter Data Sheet(PDF, ver 1.1, 439 KB ) This is a data sheet for Processor Local Bus (PLB) Arbiter. Was this document helpful? Yes \| No
04/24/2009	Processor Local Bus (PLB) v3.4 Data Sheet(PDF, ver 1.7.5, 1.42 MB ) This is the data sheet for Processor Local Bus (PLB) v3.4. Was this document helpful? Yes \| No

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PLBv46 Bus Structure

Date	Name
09/21/2010	Processor Local Bus (PLB) v4.6 (v1.05a) Data Sheet(PDF, ver 1.3, 1.18 MB ) The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers. Was this document helpful? Yes \| No

Date

Name

09/21/2010

Processor Local Bus (PLB) v4.6 (v1.05a) Data Sheet(PDF, ver 1.3, 1.18 MB )

The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers.

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