PLBv46 Bus Structure

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PLBv46 Bus Structure

Date	Name

09/21/2010	Processor Local Bus (PLB) v4.6 (v1.05a) Data Sheet(PDF, ver 1.3, 1.18 MB ) The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers. Was this document helpful? Yes \| No

Date

Name

09/21/2010

Processor Local Bus (PLB) v4.6 (v1.05a) Data Sheet(PDF, ver 1.3, 1.18 MB )

The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers.

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