Displays

This guide provides information about the Xilinx LogiCORE™ IP DisplayPort core. This guide describes how to control the core by outlining the key interfaces, detailing the configuration space, and providing an operational overview. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP DisplayPort™ interconnect protocol is designed for transmission and reception of serial-digital video at two standard rates of 1.62 Gbps and 2.7 Gbps for consumer and professional displays. DisplayPort is a high-speed serial interface standard supported by industry leaders in consumer HDTV, PC laptop and PC Monitors. This protocol replaces DVI and HDMI outside and LVDS inside the box for higher resolution, higher frame rate and color bit depth display. This document contains information about the AXI4 version of the core.

This application note describes the implementation of a DisplayPort&trade sink core and policy maker reference design targeted for the Spartan®-6 FPGA Consumer Video Kit (CVK).

Design File(s):

• xapp593_DisplayPort_Sink.zip

The LogiCORE™ IP Sony/Philips Digital Interconnect Format (SPDIF) core is a digital audio interface controller that implements the International Electronic Commission (IEC) 60958-3 interface for transmitting and receiving audio data. This document contains information about the AXI4 version of the core.

This guide provides information about the Xilinx LogiCORE™ IP DisplayPort core. This guide describes how to control the core by outlining the key interfaces, detailing the configuration space, and providing an operational overview. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP DisplayPort™ interconnect protocol is designed for transmission and reception of serial-digital video for consumer and professional displays. DisplayPort is a high-speed serial interface standard supported by PC chipsets, GPU’s and display controllers, HDTV and monitors from industry leaders and major silicon manufacturers. This document contains information about the AXI4 version of the core.

This application note describes the implementation of a DisplayPort™ source core and policy maker reference design targeted for the Spartan®-6 FPGA Consumer Video Kit (CVK).

Design File(s):

• xapp493_DisplayPort_SPM.zip

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the LogiCORE IP DisplayPort Core.