PCI Express ( PCIe )

The LogiCORE™ IP 7 Series FPGAs Integrated Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with 7 series FPGAs. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint configurations at speeds up to 5 Gb/s (Gen2), all of which are compliant with the PCI Express Base Specification, rev. 2.1. This solution supports the AXI4-Stream interface for the customer user interface.

This guide describes the function and operation of the 7 Series FPGAs Integrated Block for PCI Express®, including how to design, customize, and implement it. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint configurations at speeds up to 5.0 Gb/s (Gen2), all of which are compliant with the PCI Express Base Specification, rev. 2.1. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Release Notes and Known Issues Answer Record is for the 7 Series Integrated Block for PCI Express, first released in ISE Design Suite 13.1 and contains the following information:

• General Information
• New Features
• Supported Devices
• Resolved Issues
• Known Issues

The LogiCORE™ IP 7 Series FPGAs Integrated Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with 7 series FPGAs. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint configurations at speeds up to 5 Gb/s (Gen2), all of which are compliant with the PCI Express Base Specification, rev. 2.1. This solution supports the AXI4-Stream interface for the customer user interface.

This guide describes the function and operation of the 7 Series FPGAs Integrated Block for PCI Express®, including how to design, customize, and implement it. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint configurations at speeds up to 5.0 Gb/s (Gen2), all of which are compliant with the PCI Express Base Specification, rev. 2.1. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Release Notes and Known Issues Answer Record is for the 7 Series Integrated Block for PCI Express, first released in ISE Design Suite 13.1 and contains the following information:

• General Information
• New Features
• Supported Devices
• Resolved Issues
• Known Issues

This guide describes the function and operation of the 7 Series FPGAs Integrated Block for PCI Express®, including how to design, customize, and implement it. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint configurations at speeds up to 5.0 Gb/s (Gen2), all of which are compliant with the PCI Express Base Specification, rev. 2.1. This solution supports the AXI4-Stream interface for the customer user interface.

The LogiCORE™ IP 7 Series FPGAs Integrated Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with 7 series FPGAs. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint configurations at speeds up to 5 Gb/s (Gen2), all of which are compliant with the PCI Express Base Specification, rev. 2.1. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Release Notes and Known Issues Answer Record is for the 7 Series Integrated Block for PCI Express, first released in ISE Design Suite 13.1 and contains the following information:

• General Information
• New Features
• Supported Devices
• Resolved Issues
• Known Issues

Data sheet for the Virtex®-6 FPGA Integrated Block for PCI Express® core. This solution supports the AXI4-Stream interface for the customer user interface.

This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

Datasheet for the Virtex®-6 FPGA Integrated Block for PCI Express®. This solution supports the AXI4-Stream interface for the customer user interface.

This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

Datasheet for the Virtex®-6 FPGA Integrated Block for PCI Express®. This solution supports the AXI4-Stream interface for the customer user interface.

This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

Datasheet for the Virtex®-6 FPGA Integrated Block for PCI Express®. This solution supports the legacy TRN interface for the customer user interface.

This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the legacy TRN interface for the customer user interface.

This Release Notes and Known Issues Answer Record is for the Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express (AXI) first released in ISE Design Suite 13.1.

This guide describes the function and operation of the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express®, including how to design, customize, and implement it. The 1-lane Endpoint block supports speeds up to 2.5 Gb/s and is compliant with the PCI Express Base Specification, rev. 1.1. This solution supports the AXI4-Stream interface for the customer user interface.

Data sheet for the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Release Notes and Known Issues Answer Record is for the AXI Interface version of the Spartan-6 FPGA Integrated Block for PCI Express, first released in ISE Design Suite 12.3.

The LogiCORE™ IP Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Spartan-6 FPGA devices. The Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1. This solution supports AXI4-Stream for the customer user interface.

This guide describes the function and operation of the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express®, including how to design, customize, and implement it. The 1-lane Endpoint block supports speeds up to 2.5 Gb/s and is compliant with the PCI Express Base Specification, rev. 1.1. This solution supports the AXI4-Stream interface for the customer user interface.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Release Notes and Known Issues Answer Record is for the AXI Interface version of the Spartan-6 FPGA Integrated Block for PCI Express, first released in ISE Design Suite 12.3.

The LogiCORE™ IP Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Spartan-6 FPGA devices. The Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1. This solution supports AXI4-Stream for the customer user interface.

This guide describes the function and operation of the Spartan®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This document contains information about the AXI4 version of the core.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Release Notes and Known Issues Answer Record is for the AXI Interface version of the Spartan-6 FPGA Integrated Block for PCI Express, first released in ISE Design Suite 12.3.

The LogiCORE™ IP Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Spartan-6 FPGA devices. The Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1.

This User Guide describes the function and operation of the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express®, including how to design, customize, and implement it.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Release Notes and Known Issues Answer Record is for the Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express first released in ISE Design Suite 12.3, and it contains the following information:

• General Information 
• New Features 
• Bug Fixes 
• Known Issues 

The LogiCORE™ IP Endpoint Block Plus for PCI Express® User Guide describes the function and operation of the core, including how to design, customize, and implement the core.

The LogiCORE™ IP Endpoint Block Plus for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex®-5 LXT/SXT/FXT/TXT FPGA devices.

This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.14, released in ISE Design Suite 12.1, and contains the following information: 

• General Information 
• New Features 
• Bug Fixes 
• Known Issues 

The LogiCORE™ IP Endpoint Block Plus for PCI Express® User Guide describes the function and operation of the core, including how to design, customize, and implement the core.

The LogiCORE™ IP Endpoint Block Plus for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex®-5 LXT/SXT/FXT/TXT FPGA devices.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.  

This Design Advisory covers the Endpoint Block Plus Wrapper which uses the Virtex-5 FPGA Integrated Block for PCI Express to create a full endpoint solution.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This white paper explores the factors of PCI Express® technology and how they affect the performance of a system. This document also provides performance results from two systems that use the Xilinx® Endpoint Block Plus Wrapper for PCI Express in the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express designs.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This Release Notes and Known Issues Answer Record is for the LogiCORE Endpoint v3.7 for PCI Express, released in ISE Design Suite 12.1, and contains the following information: 

• General Information 
• New Features 
• Bug Fixes 
• Known Issues 

This guide describes the function and operation of the Endpoint solutions for PCI Express (PCIe®), including how to design, customize, and implement the core.

This guide provides information about generating an Endpoint core for PCI Express (PCIe®), customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

This is the data sheet for the LogiCORE™ IP Endpoint v3.7 for PCI Express® core.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

To communicate that Xilinx is modifying the offerings associated with these LogiCORE™ IP products.

The LogiCORE™ IP Endpoint PIPE (PHY Interface) for PCI Express® 1-lane core is a high-bandwidth scalable and reliable serial interconnect intellectual property building block for use with the Spartan®-3, Spartan-3E, and Spartan-3A FPGAs in conjunction with an external PHY device.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This user guide describes the function and operation of the Xilinx Endpoint PIPE for PCI Express® (PCIe®) core, including how to design, customize, and implement the core. The Endpoint PIPE for PCI Express core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with the Spartan®-3, Spartan-3E, and Spartan-3A FPGAs.

This document defines the functional operation of the PLBv46 Root Complex and Endpoint Bridge for PCI Express®, hereafter called PLBv46 Bridge. The PLBv46 Bridge is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) bus.

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML555 PCI/PCI Express Development Platform.

Design File(s):

• Design File for XAPP1000

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML505 Embedded Development Platform.

Design File(s):

• Design File for XAPP1030

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML507 Embedded Development Platform.

Design File(s):

• xapp1040.zip

This document defines the functional operation of the PLBv46 Root Complex and Endpoint Bridge for PCI Express®, hereafter called PLBv46 Bridge. The PLBv46 Bridge is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) bus.