Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )

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Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe) v2.4

Date	Name
01/18/2012	Spartan-6 FPGA Integrated Endpoint Block for PCI Express User Guide (AXI)(PDF, ver 1.2, 9.7 MB ) This guide describes the function and operation of the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express®, including how to design, customize, and implement it. The 1-lane Endpoint block supports speeds up to 2.5 Gb/s and is compliant with the PCI Express Base Specification, rev. 1.1. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No
01/18/2012	LogiCORE IP Spartan-6 FPGA Integrated Endpoint Block v2.4 for PCI Express Data Sheet (AXI)(PDF, ver 3.1, 203 KB ) Data sheet for the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No
07/05/2011	Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No
01/09/2012	Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions This Release Notes and Known Issues Answer Record is for the AXI Interface version of the Spartan-6 FPGA Integrated Block for PCI Express, first released in ISE Design Suite 12.3. Was this document helpful? Yes \| No

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Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe) v2.3

Date	Name
06/22/2011	LogiCORE IP Spartan-6 FPGA Integrated Endpoint Block v2.3 for PCI Express Data Sheet (AXI)(PDF, ver 3.0, 223 KB ) The LogiCORE™ IP Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Spartan-6 FPGA devices. The Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1. This solution supports AXI4-Stream for the customer user interface. Was this document helpful? Yes \| No
06/22/2011	Spartan-6 FPGA Integrated Endpoint Block for PCI Express User Guide (AXI)(PDF, ver 1.1, 11.56 MB ) This guide describes the function and operation of the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express®, including how to design, customize, and implement it. The 1-lane Endpoint block supports speeds up to 2.5 Gb/s and is compliant with the PCI Express Base Specification, rev. 1.1. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No
07/05/2011	Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No
01/09/2012	Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions This Release Notes and Known Issues Answer Record is for the AXI Interface version of the Spartan-6 FPGA Integrated Block for PCI Express, first released in ISE Design Suite 12.3. Was this document helpful? Yes \| No

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Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe) v2.2

Date	Name
12/14/2010	Spartan-6 FPGA Integrated Endpoint Block v2.2 for PCI Express Data Sheet (AXI)(PDF, ver 2.0, 168 KB ) The LogiCORE™ IP Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Spartan-6 FPGA devices. The Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1. This solution supports AXI4-Stream for the customer user interface. Was this document helpful? Yes \| No
10/05/2010	Spartan-6 FPGA Integrated Endpoint Block for PCI Express User Guide (AXI)(PDF, ver 1.0, 12.34 MB ) This guide describes the function and operation of the Spartan®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
07/05/2011	Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No
01/09/2012	Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions This Release Notes and Known Issues Answer Record is for the AXI Interface version of the Spartan-6 FPGA Integrated Block for PCI Express, first released in ISE Design Suite 12.3. Was this document helpful? Yes \| No

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Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe) v1.4

Date	Name
09/21/2010	Spartan-6 FPGA Integrated Endpoint Block v1.4 for PCI Express Data Sheet(PDF, ver 4.0, 170 KB ) The LogiCORE™ IP Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Spartan-6 FPGA devices. The Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1. Was this document helpful? Yes \| No
04/19/2010	Spartan-6 FPGA Integrated Endpoint Block for PCI Express User Guide(PDF, ver 3.0, 7.67 MB ) This User Guide describes the function and operation of the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express®, including how to design, customize, and implement it. Was this document helpful? Yes \| No
07/05/2011	Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No
08/11/2011	Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues This Release Notes and Known Issues Answer Record is for the Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express first released in ISE Design Suite 12.3, and it contains the following information: General Information New Features Bug Fixes Known Issues For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025): http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf Was this document helpful? Yes \| No

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