Spartan-6 FPGA Integrated Endpoint Block for PCI Express

The LogiCORE™ IP Spartan®-6 FPGA Integrated Endpoint Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Spartan-6 FPGA devices. The Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1.

This User Guide describes the function and operation of the Spartan®-6 Integrated Endpoint Block for PCI Express (PCIe®) core, including how to design, customize, and implement the core.

Keywords: Design Advisory, endpoint, PCIe

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

キーワード : Design Advisory, endpoint, PCIe, デザイン アドバイザリ, エンドポイント, PCI Express

デザイン アドバイザリ アンサーは、現在進行中のデザインに影響する重要な問題に対して作成され、ザイリンクス アラート通知システムに含められます。