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Virtex-5 Endpoint Block Plus Wrapper for PCI Express ( PCIe )

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Virtex-5 Endpoint Block Plus Wrapper for PCI Express ( PCIe )

DateName
04/19/2010 LogiCORE IP Endpoint Block Plus v1.14 for PCI Express User Guide(PDF, ver 14.0, 4.86 MB )

The LogiCORE™ IP Endpoint Block Plus for PCI Express® User Guide describes the function and operation of the core, including how to design, customize, and implement the core.

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06/22/2011 LogiCORE IP Endpoint Block Plus v1.15 for PCI Express Data Sheet(PDF, ver 14.0, 461 KB )

The LogiCORE™ IP Endpoint Block Plus for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex®-5 LXT/SXT/FXT/TXT FPGA devices.

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09/16/2010 Endpoint Block Plus Wrapper v1.14 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1

This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.14, released in ISE Design Suite 12.1, and contains the following information: 

  • General Information 
  • New Features 
  • Bug Fixes 
  • Known Issues 
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

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06/22/2011 LogiCORE IP Endpoint Block Plus v1.15 for PCI Express User Guide(PDF, ver 15.0, 6.05 MB )

The LogiCORE™ IP Endpoint Block Plus for PCI Express® User Guide describes the function and operation of the core, including how to design, customize, and implement the core.

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04/19/2010 LogiCORE IP Endpoint Block Plus v1.14 for PCI Express Data Sheet(PDF, ver 13.0, 435 KB )

The LogiCORE™ IP Endpoint Block Plus for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex®-5 LXT/SXT/FXT/TXT FPGA devices.

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07/05/2011 Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record


Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.  

This Design Advisory covers the Endpoint Block Plus Wrapper which uses the Virtex-5 FPGA Integrated Block for PCI Express to create a full endpoint solution.

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11/20/2009 XAPP1022 - Using the Memory Endpoint Test Driver (MET) with the Programmed Input/Output Example Design for PCI Express Endpoint Cores Application Note(PDF, ver 2.0, 3.95 MB )

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

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10/22/2007 XAPP1002 - Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE(PDF, ver 1.0, 1.27 MB )

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

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09/04/2008 WP350 - Understanding Performance of PCI Express Systems(PDF, ver 1.1, 359 KB )

This white paper explores the factors of PCI Express® technology and how they affect the performance of a system. This document also provides performance results from two systems that use the Xilinx® Endpoint Block Plus Wrapper for PCI Express in the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express designs.

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