Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )

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Virtex-6 FPGA Integrated Block for PCI Express ( PCIe ) v2.5

Date	Name
01/18/2012	LogiCORE IP Virtex-6 FPGA Integrated Block v2.5 for PCI Express Data Sheet (AXI)(PDF, ver 4.1, 220 KB ) Data sheet for the Virtex®-6 FPGA Integrated Block for PCI Express® core. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No
01/18/2012	Virtex-6 FPGA Integrated Block for PCI Express User Guide (AXI)(PDF, ver 1.3, 13.78 MB ) This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No

Date	Name
02/02/2012	Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No
06/22/2011	LogiCORE IP Virtex-6 FPGA Integrated Block v2.4 for PCI Express Data Sheet (AXI)(PDF, ver 4.0, 247 KB ) Datasheet for the Virtex®-6 FPGA Integrated Block for PCI Express®. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No
06/22/2011	Virtex-6 FPGA Integrated Block for PCI Express User Guide (AXI)(PDF, ver 1.2, 15.88 MB ) This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No

Date	Name
02/02/2012	Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No
03/01/2011	LogiCORE IP Virtex-6 FPGA Integrated Block v2.3 for PCI Express Data Sheet (AXI)(PDF, ver 3.0, 230 KB ) Datasheet for the Virtex®-6 FPGA Integrated Block for PCI Express®. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No
03/01/2011	Virtex-6 FPGA Integrated Block for PCI Express User Guide (AXI)(PDF, ver 1.1, 15.92 MB ) This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the AXI4-Stream interface for the customer user interface. Was this document helpful? Yes \| No

Date	Name
02/02/2012	Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No
03/01/2011	LogiCORE IP Virtex-6 FPGA Integrated Block v1.7 for PCI Express Data Sheet(PDF, ver 6.0, 227 KB ) Datasheet for the Virtex®-6 FPGA Integrated Block for PCI Express®. This solution supports the legacy TRN interface for the customer user interface. Was this document helpful? Yes \| No
09/21/2010	Virtex-6 FPGA Integrated Block for PCI Express User Guide(PDF, ver 5.1, 12.33 MB ) This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the legacy TRN interface for the customer user interface. Was this document helpful? Yes \| No
12/02/2011	Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Release Notes and Known Issues This Release Notes and Known Issues Answer Record is for the Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express (AXI) first released in ISE Design Suite 13.1. Was this document helpful? Yes \| No