Virtex-6 FPGA Integrated Endpoint Block for PCI Express

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Virtex-6 FPGA Integrated Endpoint Block for PCI Express

Name	Doc Version	Size	Date

Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express View Document Details Keywords: Design Advisory, root port, endpoint, PCIe Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes \| No	NA	NA	11/18/2009
Virtex-6 FPGA Integrated Block v1.3 for PCI Express User Guide (PDF) View Document Details This guide describes the function and operation of the Virtex®-6 Integrated Block for PCI Express (PCIe®) core, including how to design, customize, and implement the core. Was this document helpful? Yes \| No	3.0	6.14 MB	09/16/2009
Virtex-6 FPGA Integrated Block v1.3 for PCI Express Data Sheet (PDF) View Document Details The LogiCORE™ IP Virtex®-6 Integrated Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex-6 FPGA devices. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint operation at up to Gen2 speed, all of which are compliant with the PCI Express Base Specification v2.0. Was this document helpful? Yes \| No	2.0	769 KB	09/16/2009
Virtex-6 FPGA Integrated Block Wrapper for PCI Express のデザインアドバイザリ View Document Details キーワード : Design Advisory, root port, endpoint, PCIe, デザインアドバイザリ, ルートポート, エンドポイント, PCI Express デザインアドバイザリアンサーは、現在進行中のデザインに影響する重要な問題に対して作成され、ザイリンクスアラート通知システムに含められます。 Was this document helpful? Yes \| No	NA	NA	11/18/2009

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