PCI

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target v5.166 for PCI-X™ User Guide provides information about the Xilinx® core interface for Peripheral Component Interconnect Extended (PCI-X), targeting devices based on the Virtex™ FPGA architecture.

The LogiCORE™ IP Initiator/Target for PCI-X™ Getting Started Guide provides information about the interface for Peripheral Component Interconnect Extended (PCI-X), which provides a fully verified, pre-implemented PCI-X bus interface targeting devices based on the Virtex®-5 FPGA architecture.

This LogiCORE™ IP Initiator/Target v6.8 for PCI-X™ User Guide provides information about the Xilinx® core interface for Peripheral Component Interconnect Extended (PCI-X), which provides a fully verified, pre-implemented PCI-X bus interface targeting devices based on the Virtex® FPGA architecture.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target v3.167 for PCI™ user guide provides a comprehensive reference for use during the design phase of a project.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The LogiCORE™ IP Initiator/Target v5 and v6 for PCI®-X core interface is a pre-implemented and fully tested module for Xilinx® FPGAs.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The LogiCORE™ IP Initiator/Target v3.167 for PCI™ user guide provides a comprehensive reference for use during the design phase of a project.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The Initiator/Target core for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target v3.167 for PCI™ user guide provides a comprehensive reference for use during the design phase of a project.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

This Release Notes and Known Issues Answer Record is for the LogiCORE IP Initiator, Target v4.12 for PCI , released in ISE Design Suite 12.1, and contains the following information: 

• General Information 
• New Features 
• Bug Fixes 
• Known Issues 

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target for PCI™ User Guide provides information about the LogiCORE interface for Peripheral Component Interconnect (PCI), which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. The guide serves as a comprehensive reference for use during the design phase of a project.

The 64-Bit Initiator/Target Core v3 and v4 for PCI™ is a pre-implemented and fully tested module for Xilinx® FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

The LogiCORE™ IP Initiator/Target v5.166 for PCI-X™ User Guide provides information about the Xilinx® core interface for Peripheral Component Interconnect Extended (PCI-X), targeting devices based on the Virtex™ FPGA architecture.

This LogiCORE™ IP Initiator/Target v6.8 for PCI-X™ User Guide provides information about the Xilinx® core interface for Peripheral Component Interconnect Extended (PCI-X), which provides a fully verified, pre-implemented PCI-X bus interface targeting devices based on the Virtex® FPGA architecture.

The LogiCORE™ IP Initiator/Target v5 and v6 for PCI®-X core interface is a pre-implemented and fully tested module for Xilinx® FPGAs.

The LogiCORE™ IP Initiator/Target for PCI-X™ Getting Started Guide provides information about the interface for Peripheral Component Interconnect Extended (PCI-X), which provides a fully verified, pre-implemented PCI-X bus interface targeting devices based on the Virtex®-5 FPGA architecture.

The PCI-X™ Getting Started Guide provides information about the LogiCORE™ IP Peripheral Component Interconnect Extended (PCI-X) v5.166 interface, which provides a fully verified, pre-implemented PCI-X bus interface targeting devices based on the Virtex® device architecture.

This is the data sheet for the PLBV46 PCI Full Bridge (v1.00a) core

This is the data sheet for the PLB PCI Full Bridge (v1.00a) core

This is the data sheet for the OPB PCI Full Bridge (v1.02a) core

The OPB PCI User Guide provides design information on using the OPB PCI Full Bridge core in Virtex™-II Pro, Virtex-4, and Spartan™ FPGAs.

Design File(s):

• ug241.zip