Spartan-3 Endpoint PIPE for PCI Express ( PCIe )
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Spartan-3 Endpoint PIPE for PCI Express ( PCIe )
| Date | Name |
|---|---|
| 07/23/2010 | LogiCORE IP Endpoint PIPE v1.8 for PCI Express Data Sheet(PDF, ver 2.0, 332 KB )
The LogiCORE™ IP Endpoint PIPE (PHY Interface) for PCI Express® 1-lane core is a high-bandwidth scalable and reliable serial interconnect intellectual property building block for use with the Spartan®-3, Spartan-3E, and Spartan-3A FPGAs in conjunction with an external PHY device. |
| 11/20/2009 | XAPP1022 - Using the Memory Endpoint Test Driver (MET) with the Programmed Input/Output Example Design for PCI Express Endpoint Cores Application Note(PDF, ver 2.0, 3.95 MB )
This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®. Design File(s): |
| 10/22/2007 | XAPP1002 - Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE(PDF, ver 1.0, 1.27 MB )
This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices. Design File(s): |
| 07/23/2010 | LogiCORE IP Endpoint Pipe v1.8 for PCI Express User Guide(PDF, ver 2.0, 2.93 MB )
This user guide describes the function and operation of the Xilinx Endpoint PIPE for PCI Express® (PCIe®) core, including how to design, customize, and implement the core. The Endpoint PIPE for PCI Express core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with the Spartan®-3, Spartan-3E, and Spartan-3A FPGAs. |
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