RapidIO Logical (I/O) and Transport Layer Interface Core

Subscribe to Alerts for notification of new or changed documents related to your product of interest. If you have a question about Xilinx documentation, please open a case with Technical Support.

RapidIO Logical (I/O) and Transport Layer Interface Core

Name	Doc Version	Size	Date

RapidIO Logical (I/O) and Transport Layer Interface v4.4 Data Sheet (PDF) View Document Details The LogiCORE™ IP RapidIO Logical (I/O) and Transport Layer Interface can be used to build a customized, fully compliant system with the highest possible sustained performance of 10 Gbps in each direction. The core is compliant with the Logical Input/Output and Common Transport Specification v1.3. Was this document helpful? Yes \| No	6.5	470 KB	06/27/2008
LogiCORE IP RapidIO Logical I/O and Transport Layer v4.4 User Guide (PDF) View Document Details This guide provides information for generating a Xilinx LogiCORE™ IP RapidIO Logical (I/O) and Transport Layer Interface core. Was this document helpful? Yes \| No	5.5	1.06 MB	06/27/2008
Serial RapidIO v4.4 Getting Started Guide (PDF) View Document Details This guide contains information for generating the Xilinx LogiCORE™ IP Serial RapidIO Endpoint solution, which includes the Serial RapidIO Physical Layer and RapidIO Logical Layer cores. Was this document helpful? Yes \| No	5.5	743 KB	06/27/2008

top