Error Correction

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

The interleaver/de-interleaver core is appropriate for any application that requires data to be rearranged in an interleaved fashion, including many popular communications standards such as CDMA2000 and DVB Terrestrial(T), Cable(C), and Satellite(S). This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

The LogiCORE™ Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on. The core meets the requirements of most standards that employ RS codes, such as CCSDS, DVB, ETSI-BRAN, IEEE802.16, G.709, IESS-308. This document contains information about the AXI4 version of the core.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

The Turbo Convolution Code (TCC) Decoder core is used in conjunction with a TCC Encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

This is the data sheet for the 3GPP Turbo Encoder v4.0 core

The LogiCORE™ IP Viterbi Decoder User Guide provides information about generating a Viterbi decoder core and customizing and simulating the core using provided examples. It also includes advice on designing with the core and troubleshooting tips.

Design File(s):

• ug745.zip

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

The Convolution Encoder core can be used in a wide variety of error correcting applications and is typically used in conjunction with the Viterbi Decoder (DS247).

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.

The interleaver/de-interleaver core is appropriate for any application that requires data to be rearranged in an interleaved fashion, including many popular communications standards such as CDMA2000 and DVB Terrestrial(T), Cable(C), and Satellite(S).

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

The Xilinx LogiCORE™ IP LTE DL Channel Encoder core provides designers with an LTE Downlink Channel Encoding block for the 3GPP TS 36.212 v9.0.0 Multiplexing and Channel Coding specification.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems such as communications systems and disk drives where data is transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

Convolution encoding is used to encode data prior to transmission over a channel. The received data is decoded by the classic Viterbi decoder. This document contains information about the AXI4 version of the core.

The 3GPP Mixed Mode Turbo Decoder LogiCORE™ provides a flexible turbo convolutional decode function for both LTE and WCDMA air interfaces. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. Soft errors are unintended changes to the values stored in state elements caused by ionizing radiation.

The Convolution Encoder core can be used in a wide variety of error correcting applications and is typically used in conjunction with the Viterbi Decoder (DS247).

Convolution encoding is used to encode data prior to transmission over a channel. The received data is decoded by the classic Viterbi decoder. This document contains information about the AXI4 version of the core.

The Virtex™-5 FPGA CRC Wizard User Guide describes the function and operation of the LogiCORE™ IP Cyclic Redundancy Check (CRC) wizard for the Virtex-5 LXT, SXT, and FXT platforms.

The LogiCORE™ IP Virtex™-5 FPGA Cyclic Redundancy Check wizard provides a LocalLink wrapper for the CRC integrated block available in the Virtex-5 LXT, SXT, and FXT platforms and can be customized to suit a wide variety of requirements.

To communicate that Xilinx is discontinuing certain Development Systems products.

This is the data sheet for Additive White Gaussian Noise (AWGN) Core

The interleaver/de-interleaver core is appropriate for any application that requires data to be rearranged in an interleaved fashion, including many popular communications standards such as CDMA2000 and DVB Terrestrial(T), Cable(C), and Satellite(S).

The interleaver/de-interleaver core is appropriate for any application that requires data to be rearranged in an interleaved fashion, including many popular communications standards such as CDMA2000 and DVB Terrestrial(T), Cable(C), and Satellite(S). This document contains information about the AXI4 version of the core.

The Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The LogiCORE™ Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on. The core meets the requirements of most standards that employ RS codes, such as CCSDS, DVB, ETSI-BRAN, IEEE802.16, G.709, IESS-308. This document contains information about the AXI4 version of the core.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems such as communications systems and disk drives where data is transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

This is the data sheet for 3GPP2 Turbo Decoder v1.0

This is the data sheet for 3GPP2 Turbo Decoder v2.1.

The Turbo Convolution Code (TCC) Decoder core is used in conjunction with a TCC Encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

This is the data sheet for 3GPP2 Turbo Encoder v2.0

This is the data sheet for the 3GPP Turbo Encoder v4.0 core

This core performs decoding for the turbo product codes listed in the IEEE 802.16 and 802.16a standards.

This core performs TPC encoding as defined in the IEEE 802.16 and 802.16a standards.

The LogiCORE™ IP Viterbi Decoder User Guide provides information about generating a Viterbi decoder core and customizing and simulating the core using provided examples. It also includes advice on designing with the core and troubleshooting tips.

Design File(s):

• ug745.zip

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

The 3GPP LTE Turbo Encoder v1.0 core has a bit accurate C model designed for system modeling. This allows the user to model the core performance.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. A soft error is an unintended change to the state of memory bits caused by ionizing radiation.

This guide provides information about the Soft Error Mitigation (SEM) Controller. This guide describes how to design with the core by outlining the key interfaces, detailing its behaviors, and providing an operational overview.

The LogiCORE™ IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx FPGAs. Soft errors are unintended changes to the values stored in state elements caused by ionizing radiation.

The 3GPP Mixed Mode Turbo Decoder LogiCORE™ provides a flexible turbo convolutional decode function for both LTE and WCDMA air interfaces. This document contains information about the AXI4 version of the core.