Ethernet

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

The LogiCORE™ IP Media Indepenent Interface (MII) to Reduced Media Independent (RMII) design provides the RMII between RMII-compliant ethernet physical media devices (PHY) and Xilinx 10/100 Mb/s ethernet cores such as the XPS LL TEMAC and XPS Ethernet Lite.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed full-duplex 10-Gb/s Ethernet Media Access Controller (MAC) solution that enables the design of high-speed Ethernet systems and subsystems.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed full-duplex 10-Gb/s Ethernet Media Access Controller (MAC) solution that enables the design of high-speed Ethernet systems and subsystems.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA core forms a seamless interface between the Xilinx@reg; 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7, and Virtex-6 HXT FPGAs.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper (V6EMAC) comprises the 10/100/1000 Mb/s MAC and the 1000BASE-X PCS/PMA or SGMII IP Cores, which are fully-verified designs that support Verilog-HDL and VHDL. In addition, the example design provided with the core is in both Verilog and VHDL. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gb/s Ethernet Media Access Controller (MAC) solution enabling the design of high-speed Ethernet systems and subsystems. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet MAC and the 10/100 Mb/s Ethernet MAC IP core. All cores support half-duplex and full-duplex operation. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Ethernet Statistics core provides a user-configurable collection of statistical counters that can be used to gather network traffic statistics for Xilinx® Ethernet Media Access Controller (MAC) products.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10-Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx Virtex®-6, Virtex-7, and Kintex™-7 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA (10GBASE-R) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gbps-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7 and Virtex-6 HXT

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution.

The Ethernet Statistics v3.5 User Guide describes the function and operation of the Xilinx® Ethernet Statistics core, including information about designing, customizing, and implementing the core.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gb/s Ethernet Media Access Controller (MAC) solution enabling the design of high-speed Ethernet systems and subsystems. This document contains information about the AXI4 version of the core.

This document provides the design specification for the XPS_LL_TEMAC soft Ethernet core.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

The Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC (V6EMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The Virtex®-4 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide provides information about generating an embedded Tri-Mode Ethernet MAC wrapper, customizing and simulating the wrapper files utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP XAUI Getting Started Guide provides instructions for generating the core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gbps Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA families.

The XAUI v9.2 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide provides information about generating an embedded Tri-Mode Ethernet MAC for Virtex-5 FPGA devices, customizing and simulating the wrapper files utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This white paper describes the Virtex®-6 FPGA Connectivity Kit (DK-V6-CONN-G) and the Spartan®-6 FPGA Connectivity Kit (DK-S6-CONN-G) that engineers can use to jump-start their connectivity-based designs.

The Ethernet 1000Base-X PCS/PMA or SGMII Getting Started Guide provides information about generating an Ethernet 1000BASE-X PCS/PMA core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The 10-Gigabit Ethernet MAC Getting Started Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ Virtex®-4 Embedded Tri-Mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper files for the Tri-Mode Ethernet MAC in Virtex-4 FX devices using the Xilinx CORE Generator™.

The LogiCORE™ IP Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-5 LXT, SXT, FXT and TXT FPGAs using the Xilinx® CORE Generator™ software.

This Getting Started Guide provides information about generating, customizing and simulating wrappers for the embedded Tri-Mode Ethernet MAC blocks in Virtex®-6 FPGA devices. This guide also describes running the design files through implementation using Xilinx® tools.

The LogiCORE™ IP Ethernet Statistics Getting Started Guide provides information about generating an Ethernet Statistics core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx FPGA families.

Keywords: Design Advisory, TEMAC, MAC, ethernet

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This guide describes the Embedded Tri-Mode Ethernet Media Access Controller (MAC) available in the Virtex®-4 FX family.

The RXAUI Getting Started Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This is the data sheet for the XPS Ethernet Lite Media Access Controller (v4.00a) core.

This Getting Started Guide provides information about generating, customizing and simulating wrappers for the embedded Tri-Mode Ethernet MAC blocks in Virtex®-6 FPGA devices. This guide also describes running the design files through implementation using Xilinx® tools.

The Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide provides information about generating an embedded Tri-Mode Ethernet MAC for Virtex-5 FPGA devices, customizing and simulating the wrapper files utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The XAUI v10.1 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx® FPGA families.

This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller (MAC) available in Virtex®-5 devices.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC solution is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-5 LXT, SXT, FXT and TXT FPGAs using the Xilinx® CORE Generator™ software.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet MAC and the 10/100 Mb/s Ethernet MAC IP core. All cores support half-duplex and full-duplex operation. This document contains information about the AXI4 version of the core.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The Quad Serial Gigabit Media Independent Interface (QSGMII) core provides a flexible solution for combining four Serial Gigabit Media Independent Interfaces (SGMII) into a single 5 Gigabits per second (Gb/s) Interface, to significantly reduce the number of Input Outputs (I/Os). This core supports Cisco QSGMII specification Version 1.2 (EDCS-540123).

The Quad Serial Gigabit Media Independent Interface (QSGMII) core provides a flexible solution for combining four Serial Gigabit Media Independent Interfaces (SGMII) into a single 5 Gigabits per second (Gb/s) Interface, to significantly reduce the number of Input Outputs (I/Os). This core supports Cisco QSGMII specification Version 1.2 (EDCS-540123).

The Xilinx® LogiCORE™ IP SMPTE2022-5/6 Video over IP Receiver is a module for broadcast applications that requires bridging between SMPTE video connectivity standards (SD/HD/3G-SDI) and 10Gb/s networks. The module is capable of recovering IP packets lost to network transmission errors and ensure the picture quality of uncompressed, high bandwidth professional video. This document contains information about the AXI4 version of the core.

The eXtended Attachment Unit Interface (XAUI) core is a high-performance, low-pin count 10-Gb/s interface intended to allow physical separation between the data link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 Field Programmable Gate Array (FPGA) devices.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

The Xilinx LogiCORE™ IP SMPTE2022-5/6 Video over IP Transmitter is a module for broadcast applications that requires bridging between SMPTE video connectivity standards (SD/HD/3G-SDI) and 10 Gb/s networks. It is capable of mapping SD/HD/3G-SDI video streams into Ethernet packets and adding systematically generated redundant data. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet MAC and the 10/100 Mb/s Ethernet MAC IP core. All cores support half-duplex and full-duplex operation. This document contains information about the AXI4 version of the core.

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gb/s Ethernet Media Access Controller (MAC) solution enabling the design of high-speed Ethernet systems and subsystems. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10 Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx® 7 series and Virtex®-6 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper (V6EMAC) comprises the 10/100/1000 Mb/s MAC and the 1000BASE-X PCS/PMA or SGMII IP Cores, which are fully-verified designs that support Verilog-HDL and VHDL. In addition, the example design provided with the core is in both Verilog and VHDL. This document contains information about the AXI4 version of the core.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gb/s Ethernet Media Access Controller (MAC) solution enabling the design of high-speed Ethernet systems and subsystems. This document contains information about the AXI4 version of the core.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The 10-Gigabit Ethernet MAC Getting Started Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This Answer Record contains the Release Notes for the LogiCORE IP 10-Gigabit Ethernet MAC v10.1 core, which was released in ISE design tools 12.1, and contains the following information: 

• New Features 
• Bug Fixes 
• Known Issues  

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Xilinx 10G Ethernet Cores: 10G Ethernet MAC, XAUI, RXAUI and10G Ethernet PCS/PMA.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed full-duplex 10-Gb/s Ethernet Media Access Controller (MAC) solution that enables the design of high-speed Ethernet systems and subsystems.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed full-duplex 10-Gb/s Ethernet Media Access Controller (MAC) solution that enables the design of high-speed Ethernet systems and subsystems.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gb/s Ethernet Media Access Controller (MAC) solution enabling the design of high-speed Ethernet systems and subsystems. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gb/s Ethernet Media Access Controller (MAC) solution enabling the design of high-speed Ethernet systems and subsystems. This document contains information about the AXI4 version of the core.

The 10-Gigabit Ethernet MAC User Guide provides information about generating a LogiCORE™ IP 10-Gigabit Ethernet MAC core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

This Answer Record contains the Release Notes for the LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v10.4 Core (released in the ISE Design Suite 12.1), and includes the following:  

• New Features  
• Resolved Issues  
• Known Issues 

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at: 
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

The Ethernet 1000Base-X PCS/PMA or SGMII Getting Started Guide provides information about generating an Ethernet 1000BASE-X PCS/PMA core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

This is the data sheet for the OPB Ethernet Media Access Controller (EMAC) (v1.04a) core

The LogiCORE™ IP Ethernet Statistics core provides a user-configurable collection of statistical counters that can be used to gather network traffic statistics for Xilinx® Ethernet Media Access Controller (MAC) products.

The Ethernet Statistics v3.5 User Guide describes the function and operation of the Xilinx® Ethernet Statistics core, including information about designing, customizing, and implementing the core.

This Answer Record contains the Release Notes for the LogiCORE IP Ethernet Statistics v3.4 Core, which was released in ISE 12.1 software and includes the following: 

• New Features 
• Bug Fixes  
• Known Issues 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: 
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

The LogiCORE™ IP Ethernet Statistics Getting Started Guide provides information about generating an Ethernet Statistics core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools.

This is the data sheet for the OPB Ethernet Lite Media Access Controller (v1.01b) core

Product specification for PLB 1-Gigabit Ethernet Media Access Controller (MAC) with DMA - PRELIMINARY.

The LogiCORE™ Virtex®-4 Embedded Tri-Mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper files for the Tri-Mode Ethernet MAC in Virtex-4 FX devices using the Xilinx CORE Generator™.

The Virtex®-4 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide provides information about generating an embedded Tri-Mode Ethernet MAC wrapper, customizing and simulating the wrapper files utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This Answer Record contains the Release Notes for the LogiCORE IP Embedded Tri-mode Ethernet MAC Wrapper v1.7, which was released in ISE Design Suite 12.1 and includes the following: 

• General Information 
• New Features  
• Bug Fixes  
• Known Issues  

The Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide provides information about generating an embedded Tri-Mode Ethernet MAC for Virtex-5 FPGA devices, customizing and simulating the wrapper files utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-5 LXT, SXT, FXT and TXT FPGAs using the Xilinx® CORE Generator™ software.

The Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide provides information about generating an embedded Tri-Mode Ethernet MAC for Virtex-5 FPGA devices, customizing and simulating the wrapper files utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller (MAC) available in Virtex®-5 devices.

The LogiCORE™ IP Virtex®-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-5 LXT, SXT, FXT and TXT FPGAs using the Xilinx® CORE Generator™ software.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gbps Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA families.

The LogiCORE™ IP XAUI Getting Started Guide provides instructions for generating the core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

The XAUI v9.2 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Xilinx 10G Ethernet Cores: 10G Ethernet MAC, XAUI, RXAUI and10G Ethernet PCS/PMA.

This Answer Record contains the Release Notes for the LogiCORE IP XAUI v9.2 Core, which was released in the ISE Design Suite 12.1, and includes the following: 

• New Features 
• Bug Fixes  
• Known Issues 

The XAUI v10.1 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

The eXtended Attachment Unit Interface (XAUI) core is a high-performance, low-pin count 10-Gb/s interface intended to allow physical separation between the data link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 Field Programmable Gate Array (FPGA) devices.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

This is the data sheet for the XPS Ethernet Lite Media Access Controller (v4.00a) core.

This document provides the design specification for the XPS_LL_TEMAC soft Ethernet core.

The LogiCORE™ IP Media Indepenent Interface (MII) to Reduced Media Independent (RMII) design provides the RMII between RMII-compliant ethernet physical media devices (PHY) and Xilinx 10/100 Mb/s ethernet cores such as the XPS LL TEMAC and XPS Ethernet Lite.

This is the data sheet for the PLB Ethernet Media Access Controller (PLB_EMAC) - (v1.01a) core.

This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller (MAC) available in Virtex®-5 devices.

This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v4.8, which was originally released in ISE Design Suite 12.1 and later tested for ISE Design Suite 13.1 and 14.1, and includes the following:  

• New Features 
• Bug Fixes 
• Known Issues  

This Answer Record contains the Release Notes for the LogiCORE IP Ethernet AVB Endpoint v2.3, which was released in ISE Design Suite 12.1 and includes the following: 

• General Information 
• New Features  
• Resolved Issues  
• Known Issues  

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide: 
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx FPGA families.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx® FPGA families.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet MAC and the 10/100 Mb/s Ethernet MAC IP core. All cores support half-duplex and full-duplex operation. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation.

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution.

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

This Answer Record contains the Release Notes for the LogiCORE IP Tri-Mode Ethernet MAC v4.4 Core (released in the ISE 12.1 software), v4.4 rev1 (released in ISE 12.2), and v4.4 rev2 (released as a patch below), and includes the following: 

• New Features  
• Resolved Issues 
• Known Issues  

Keywords: Design Advisory, TEMAC, MAC, ethernet

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This guide describes the Embedded Tri-Mode Ethernet Media Access Controller (MAC) available in the Virtex®-4 FX family.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet MAC and the 10/100 Mb/s Ethernet MAC IP core. All cores support half-duplex and full-duplex operation. This document contains information about the AXI4 version of the core.

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet MAC and the 10/100 Mb/s Ethernet MAC IP core. All cores support half-duplex and full-duplex operation. This document contains information about the AXI4 version of the core.

The Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Tri-Mode Ethernet MAC (TEMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

The Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC (V6EMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core.

This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software.

This Getting Started Guide provides information about generating, customizing and simulating wrappers for the embedded Tri-Mode Ethernet MAC blocks in Virtex®-6 FPGA devices. This guide also describes running the design files through implementation using Xilinx® tools.

This Getting Started Guide provides information about generating, customizing and simulating wrappers for the embedded Tri-Mode Ethernet MAC blocks in Virtex®-6 FPGA devices. This guide also describes running the design files through implementation using Xilinx® tools.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC solution is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core.

This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.4, which was released in ISE Design Suite 12.1, and includes the following: 

• General Information 
• New Features  
• Resolved Issues  
• Known Issues  

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core.

The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper (V6EMAC) comprises the 10/100/1000 Mb/s MAC and the 1000BASE-X PCS/PMA or SGMII IP Cores, which are fully-verified designs that support Verilog-HDL and VHDL. In addition, the example design provided with the core is in both Verilog and VHDL. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software.

The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper (V6EMAC) comprises the 10/100/1000 Mb/s MAC and the 1000BASE-X PCS/PMA or SGMII IP Cores, which are fully-verified designs that support Verilog-HDL and VHDL. In addition, the example design provided with the core is in both Verilog and VHDL. This document contains information about the AXI4 version of the core.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10-Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx Virtex®-6, Virtex-7, and Kintex™-7 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The RXAUI Getting Started Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This Answer Record contains the Release Notes for the LogiCORE IP RXAUI v1.2 Core, which was released in the 12.1 ISE software, and includes the following: 

• New Features 
• Bug Fixes  
• Known Issues 

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Xilinx 10G Ethernet Cores: 10G Ethernet MAC, XAUI, RXAUI and10G Ethernet PCS/PMA.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10 Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx® 7 series and Virtex®-6 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA (10GBASE-R) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gbps-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7 and Virtex-6 HXT

This Answer Record contains the Release Notes for the LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) v1.1 Core, released in ISE Design Suite 11.4, and includes the following: 

• General Information 
• New Features
• Resolved Issues
• Known Issues 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: 
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Xilinx 10G Ethernet Cores: 10G Ethernet MAC, XAUI, RXAUI and10G Ethernet PCS/PMA.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA core forms a seamless interface between the Xilinx@reg; 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7, and Virtex-6 HXT FPGAs.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Quad Serial Gigabit Media Independent Interface (QSGMII) core provides a flexible solution for combining four Serial Gigabit Media Independent Interfaces (SGMII) into a single 5 Gigabits per second (Gb/s) Interface, to significantly reduce the number of Input Outputs (I/Os). This core supports Cisco QSGMII specification Version 1.2 (EDCS-540123).

The Quad Serial Gigabit Media Independent Interface (QSGMII) core provides a flexible solution for combining four Serial Gigabit Media Independent Interfaces (SGMII) into a single 5 Gigabits per second (Gb/s) Interface, to significantly reduce the number of Input Outputs (I/Os). This core supports Cisco QSGMII specification Version 1.2 (EDCS-540123).

The LogiCORE™ IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Xilinx® LogiCORE™ IP SMPTE2022-5/6 Video over IP Receiver is a module for broadcast applications that requires bridging between SMPTE video connectivity standards (SD/HD/3G-SDI) and 10Gb/s networks. The module is capable of recovering IP packets lost to network transmission errors and ensure the picture quality of uncompressed, high bandwidth professional video. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP SMPTE2022-5/6 Video over IP Transmitter is a module for broadcast applications that requires bridging between SMPTE video connectivity standards (SD/HD/3G-SDI) and 10 Gb/s networks. It is capable of mapping SD/HD/3G-SDI video streams into Ethernet packets and adding systematically generated redundant data. This document contains information about the AXI4 version of the core.