RXAUI
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RXAUI
| Date | Name |
|---|---|
| 03/01/2011 | LogiCORE IP RXAUI v2.1 User Guide(PDF, ver 2.1, 3.67 MB )
The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools. |
| 03/01/2011 | LogiCORE IP RXAUI v2.1 Data Sheet(PDF, ver 1.3, 452 KB )
The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10-Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx Virtex®-6, Virtex-7, and Kintex™-7 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications. |
| 04/19/2010 | LogiCORE IP RXAUI v1.2 Getting Started Guide(PDF, ver 1.2, 952 KB )
The RXAUI Getting Started Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools. |
| 01/24/2011 | LogiCORE IP RXAUI v1.2 - Release Notes and Known Issues for the 12.1 ISE software
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf |
| 01/27/2011 | Design Advisory for 10G Ethernet Cores - 10G Ethernet MAC, XAUI, RXAUI, 10G Ethernet PCS/PMA
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. |
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