Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper

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Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper

Date	Name

03/01/2011	LogiCORE IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide (AXI)(PDF, ver 1.0, 5.33 MB ) The Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide describes the function and operation of the LogiCORE™ IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC (V6EMAC) solution, as well as information about designing, customizing, and implementing the solution. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
03/01/2011	Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide(PDF, ver 1.3, 6.4 MB ) This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760. Was this document helpful? Yes \| No
04/19/2010	Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.4 Data Sheet(PDF, ver 3.0, 376 KB ) The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. Was this document helpful? Yes \| No
04/19/2010	Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.4 Getting Started Guide(PDF, ver 2.1, 2.95 MB ) This Getting Started Guide provides information about generating, customizing and simulating wrappers for the embedded Tri-Mode Ethernet MAC blocks in Virtex®-6 FPGA devices. This guide also describes running the design files through implementation using Xilinx® tools. Was this document helpful? Yes \| No
03/01/2011	Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.5 Getting Started Guide(PDF, ver 2.2, 2.77 MB ) This Getting Started Guide provides information about generating, customizing and simulating wrappers for the embedded Tri-Mode Ethernet MAC blocks in Virtex®-6 FPGA devices. This guide also describes running the design files through implementation using Xilinx® tools. Was this document helpful? Yes \| No
03/01/2011	Virtex-6 FPGA Embedded TEMAC Solution v2.1 Data Sheet (AXI)(PDF, ver 1.1, 918 KB ) The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC solution is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
02/17/2011	Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.4 - Release Notes and Known Issues for ISE Design Suite 12.1 This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.4, which was released in ISE Design Suite 12.1, and includes the following: General Information New Features Resolved Issues Known Issues For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf Was this document helpful? Yes \| No
03/01/2011	Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.5 Data Sheet(PDF, ver 4.0, 425 KB ) The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. Was this document helpful? Yes \| No
10/19/2011	LogiCORE IP Virtex-6 FPGA Embedded TEMAC Solution v2.2 Data Sheet (AXI)(PDF, ver 2.0, 755 KB ) The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper is comprised of the Embedded Tri-Mode Ethernet MAC primitive with additional logic to simplify and update the user interface. It is available in Virtex-6 LXT, SXT, HXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
10/19/2011	LogiCORE IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v2.2 User Guide (AXI)(PDF, ver 1.1, 4.93 MB ) The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper (V6EMAC) comprises the 10/100/1000 Mb/s MAC and the 1000BASE-X PCS/PMA or SGMII IP Cores, which are fully-verified designs that support Verilog-HDL and VHDL. In addition, the example design provided with the core is in both Verilog and VHDL. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No

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