Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper

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Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper

Name	Doc Version	Size	Date

Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.3 Getting Started Guide (PDF) View Document Details This Getting Started Guide provides information about generating, customizing and simulating wrappers for the embedded Tri-Mode Ethernet MAC blocks in Virtex®-6 FPGA devices. This guide also describes running the design files through implementation using Xilinx® tools. Was this document helpful? Yes \| No	2.0.1	2.15 MB	10/15/2009
Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.3 Data Sheet (PDF) View Document Details The LogiCORE™ IP Virtex®-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-6 LXT, SXT, and CXT FPGAs using the Xilinx® CORE Generator™ software. Was this document helpful? Yes \| No	2.0.1	356 KB	10/15/2009

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