Serial Interface

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA core forms a seamless interface between the Xilinx@reg; 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7, and Virtex-6 HXT FPGAs.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 8B/10B v7.1 User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-7, Kintex™-7, and Virtex-6 FPGA GTX transceivers and Spartan®-6 FPGA GTP transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and Kintex™-7 families (including lower power devices), Virtex-6 LXT, SXT, CXT, and HXT family (including lower power devices), and the Spartan®-6 LXT family. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and Kintex™-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 64B/66B v6.1 User Guide provides information for generating a LogiCORE™ IP Aurora 64B/66B core using Virtex®-7 and Kintex™-7 FPGA GTX transceivers and Virtex-6 FPGA GTX/GTH transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-7, Kintex™-7, and Virtex-6 LXT, SXT, and HXT devices. The core can use up to 16 Virtex-7, Kintex-7, and Virtex-6 FPGA GTX transceivers and up to 12 GTH transceivers in a Virtex-6 HXT device running at any supported line rate to provide a low-cost, general-purpose, data channel with throughput from 600 Mbps to over 194 Gbps. This document contains information about the AXI4 version of the core.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10-Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx Virtex®-6, Virtex-7, and Kintex™-7 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA (10GBASE-R) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gbps-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7 and Virtex-6 HXT

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-6 LXT, SXT, CXT, HXT, and lower power family and the Spartan®-6 LXT family. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 8B/10B v6.2 User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-6 FPGA GTX transceivers and Spartan®-6 FPGA GTP transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 64B/66B v5.1 User Guide provides information for generating a LogiCORE™ IP Aurora 64B/66B core using Virtex®-5 FPGA GTX transceivers and Virtex-6 FPGA GTX/GTH transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B v5.1 User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-5 FPGA GTP/GTX transceivers and Virtex-6 FPGA GTX transceivers. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex-5 LXT, SXT, FXT, and TXT family, the Virtex-6 LXT/SXT, CXT, and Lower Power family, and the Spartan®-6 LXT family. This user guide describes the function and operation of the LogiCORE IP Aurora 8B/10B v5.2 core and provides information about designing, customizing, and implementing the core.

The LogiCORE™ IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-5 LXT, SXT, FXT, and TXT family, the Virtex-6 LXT, SXT, CXT, and Lower Power family, and the Spartan®-6 LXT family.

The LogiCORE™ IP XAUI Getting Started Guide provides instructions for generating the core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gbps Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA families.

The XAUI v9.2 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Aurora 64B/66B core implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices.

The Aurora 8B/10B protocol is a scalable, lightweight, link-layer protocol that can be used to move data point-to-point across one or more high-speed serial lanes. The Aurora 8B/10B protocol is an open standard and is available for implementation by anyone without restriction.

This guide provides information about generating a LogiCORE™ IP Aurora 64B/66B core using high-speed serial GTX or GTH transceivers in Virtex®-5 FPGA FXT/TXT and Virtex-6 FPGA LXT/SXT/HXT families. The information includes customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

This Guide provides information about generating a LogiCORE™ IP Aurora8B/10B core using Virtex®-4 FPGA RocketIO™ multi-gigabit transceivers. The information includes customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

Xilinx offers two versions of LogiCORE™ IP Aurora cores that are distinguished by the encoding performed on the serial link: the Aurora 8B/10B core and Aurora 64B/66B core. This guide discusses their differences and provides instructions to migrate an Aurora 8B/10B core design to an Aurora 64B/66B core design.

The LogiCORE™ IP Aurora core is a high-speed serial solution based on the Aurora protocol and the Virtex®-4 FPGA RocketIO™ multi-gigabit transceivers (MGT). The core is delivered as open-source code and supports both Verilog and VHDL design environments.

The LogiCORE™ IP Aurora 8B/10B Core implements the Aurora protocol on the Virtex®-4 FX FPGA. The core can use up to 16 Virtex-4 FPGA RocketIO™ multigigabit transceivers (MGTs) running at any supported line rate to provide a low-cost, general purpose, data channel with throughput from 1.26 Gbps to over 100 Gbps.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B v4.1 Core and provides information about designing, customizing, and implementing the core.

The RXAUI Getting Started Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This specification describes the Aurora 64B/66B protocol. Aurora is a lightweight linklayer protocol that can be used to move data point-to-point across one or more high-speed serial lanes. Aurora 64B/66B is a version of the protocol using 64B/66B encoding instead of 8B/10B.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices. The core can use up to 16 Virtex-5 or Virtex-6 FPGA GTX transceivers and up to 8(1) GTH transceivers in an HXT device running at any supported line rate to provide a low cost, general purpose, data channel with throughput from 750 Mbps to over 86.78 Gbps. This document contains information about the AXI4 version of the core.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B v4.2 Core and provides information about designing, customizing, and implementing the core.

The XAUI v10.1 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Aurora 64B/66B core implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The LogiCORE™ IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-5 LXT, SXT, FXT, and TXT family, the Virtex-6 LXT, SXT, CXT, HXT, and lower-power family, and the Spartan®-6 LXT family.

This user guide describes the function and operation of the LogiCORE@trade; IP Aurora 8B/10B v5.3 core and provides information about designing, customizing, and implementing the core.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-6 LXT, SXT, and HXT, Kintex™-7, and Virtex-7 devices. This document contains information about the AXI4 version of the core.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B v6.2 core and provides information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core.

The eXtended Attachment Unit Interface (XAUI) core is a high-performance, low-pin count 10-Gb/s interface intended to allow physical separation between the data link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 Field Programmable Gate Array (FPGA) devices.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and a line rate of up to 10.3125 Gb/s on 1, 2, 4 or 8 lanes using GTX transceivers in Kintex™-7 and Virtex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The core supports sharing a GTX transceiver between a transmitter and receiver. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10 Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx® 7 series and Virtex®-6 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and Kintex™-7 families (including the -2L lower power devices); Virtex-6 LXT, SXT, CXT, HXT, and lower power families; and the Spartan®-6 LXT family. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 8B/10B User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-7, Kintex™-7, and Virtex-6 FPGA GTX transceivers and Spartan®-6 FPGA GTP transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-6 LXT, SXT, and HXT, Kintex™-7, and Virtex-7 devices. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B core and provides information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx® Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The Virtex®-5 FPGA Aurora 64B/66B core implements the Aurora protocol on Virtex-5 FXT FPGAs. The core can use up to 24 RocketIO™ GTX transceivers running at any supported line rate to provide a low cost, general purpose, data channel with throughput from 662 Mb/s to over 6.25 Gb/s.

This is the data sheet for Virtex®-5 FPGA Aurora v3.0 Core.

This is the data sheet for Virtex™-5 GTP Aurora 2.8 core.

This is the data sheet for the Aurora v3.0 core.

The LogiCORE™ IP XAUI Getting Started Guide provides instructions for generating the core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gbps Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA families.

The XAUI v9.2 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The XAUI v10.1 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

The eXtended Attachment Unit Interface (XAUI) core is a high-performance, low-pin count 10-Gb/s interface intended to allow physical separation between the data link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 Field Programmable Gate Array (FPGA) devices.

The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL.

The Aurora 8B/10B protocol is a scalable, lightweight, link-layer protocol that can be used to move data point-to-point across one or more high-speed serial lanes. The Aurora 8B/10B protocol is an open standard and is available for implementation by anyone without restriction.

The LogiCORE™ IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-5 LXT, SXT, FXT, and TXT family, the Virtex-6 LXT, SXT, CXT, and Lower Power family, and the Spartan®-6 LXT family.

The LogiCORE™ IP Aurora 8B/10B v5.1 User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-5 FPGA GTP/GTX transceivers and Virtex-6 FPGA GTX transceivers. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex-5 LXT, SXT, FXT, and TXT family, the Virtex-6 LXT/SXT, CXT, and Lower Power family, and the Spartan®-6 LXT family. This user guide describes the function and operation of the LogiCORE IP Aurora 8B/10B v5.2 core and provides information about designing, customizing, and implementing the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-6 LXT, SXT, CXT, HXT, and lower power family and the Spartan®-6 LXT family. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 8B/10B v6.2 User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-6 FPGA GTX transceivers and Spartan®-6 FPGA GTP transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 8B/10B v7.1 User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-7, Kintex™-7, and Virtex-6 FPGA GTX transceivers and Spartan®-6 FPGA GTP transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and Kintex™-7 families (including lower power devices), Virtex-6 LXT, SXT, CXT, and HXT family (including lower power devices), and the Spartan®-6 LXT family. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-5 LXT, SXT, FXT, and TXT family, the Virtex-6 LXT, SXT, CXT, HXT, and lower-power family, and the Spartan®-6 LXT family.

This user guide describes the function and operation of the LogiCORE@trade; IP Aurora 8B/10B v5.3 core and provides information about designing, customizing, and implementing the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and Kintex™-7 families (including the -2L lower power devices); Virtex-6 LXT, SXT, CXT, HXT, and lower power families; and the Spartan®-6 LXT family. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 8B/10B User Guide provides information for generating a LogiCORE IP Aurora 8B/10B core using Virtex®-7, Kintex™-7, and Virtex-6 FPGA GTX transceivers and Spartan®-6 FPGA GTP transceivers. This document contains information about the AXI4 version of the core.

Xilinx offers two versions of LogiCORE™ IP Aurora cores that are distinguished by the encoding performed on the serial link: the Aurora 8B/10B core and Aurora 64B/66B core. This guide discusses their differences and provides instructions to migrate an Aurora 8B/10B core design to an Aurora 64B/66B core design.

The LogiCORE™ IP Aurora 64B/66B core implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices.

This guide provides information about generating a LogiCORE™ IP Aurora 64B/66B core using high-speed serial GTX or GTH transceivers in Virtex®-5 FPGA FXT/TXT and Virtex-6 FPGA LXT/SXT/HXT families. The information includes customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B v4.1 Core and provides information about designing, customizing, and implementing the core.

This Answer Record contains the Release Notes for the Aurora 64B/66B v4.1 Core, released in ISE Design Suite 12.1, and includes the following: 

• New Features  
• Bug Fixes 
• Known Issues  

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

This specification describes the Aurora 64B/66B protocol. Aurora is a lightweight linklayer protocol that can be used to move data point-to-point across one or more high-speed serial lanes. Aurora 64B/66B is a version of the protocol using 64B/66B encoding instead of 8B/10B.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 64B/66B v5.1 User Guide provides information for generating a LogiCORE™ IP Aurora 64B/66B core using Virtex®-5 FPGA GTX transceivers and Virtex-6 FPGA GTX/GTH transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices. The core can use up to 16 Virtex-5 or Virtex-6 FPGA GTX transceivers and up to 8(1) GTH transceivers in an HXT device running at any supported line rate to provide a low cost, general purpose, data channel with throughput from 750 Mbps to over 86.78 Gbps. This document contains information about the AXI4 version of the core.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B v4.2 Core and provides information about designing, customizing, and implementing the core.

The LogiCORE™ IP Aurora 64B/66B core implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-7, Kintex™-7, and Virtex-6 LXT, SXT, and HXT devices. The core can use up to 16 Virtex-7, Kintex-7, and Virtex-6 FPGA GTX transceivers and up to 12 GTH transceivers in a Virtex-6 HXT device running at any supported line rate to provide a low-cost, general-purpose, data channel with throughput from 600 Mbps to over 194 Gbps. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. The LogiCORE IP Aurora 64B/66B v6.1 User Guide provides information for generating a LogiCORE™ IP Aurora 64B/66B core using Virtex®-7 and Kintex™-7 FPGA GTX transceivers and Virtex-6 FPGA GTX/GTH transceivers. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-6 LXT, SXT, and HXT, Kintex™-7, and Virtex-7 devices. This document contains information about the AXI4 version of the core.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B v6.2 core and provides information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora 64B/66B core supports the AMBA® protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex®-6 LXT, SXT, and HXT, Kintex™-7, and Virtex-7 devices. This document contains information about the AXI4 version of the core.

This user guide describes the function and operation of the LogiCORE™ IP Aurora 64B/66B core and provides information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Aurora core is a high-speed serial solution based on the Aurora protocol and the Virtex®-4 FPGA RocketIO™ multi-gigabit transceivers (MGT). The core is delivered as open-source code and supports both Verilog and VHDL design environments.

The LogiCORE™ IP Aurora 8B/10B Core implements the Aurora protocol on the Virtex®-4 FX FPGA. The core can use up to 16 Virtex-4 FPGA RocketIO™ multigigabit transceivers (MGTs) running at any supported line rate to provide a low-cost, general purpose, data channel with throughput from 1.26 Gbps to over 100 Gbps.

This Guide provides information about generating a LogiCORE™ IP Aurora8B/10B core using Virtex®-4 FPGA RocketIO™ multi-gigabit transceivers. The information includes customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The Aurora 8B/10B protocol is a scalable, lightweight, link-layer protocol that can be used to move data point-to-point across one or more high-speed serial lanes. The Aurora 8B/10B protocol is an open standard and is available for implementation by anyone without restriction.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10-Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx Virtex®-6, Virtex-7, and Kintex™-7 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The RXAUI Getting Started Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10 Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx® 7 series and Virtex®-6 FPGAs that comply with the Dune Networks and Marvell RXAUI specifications.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA (10GBASE-R) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gbps-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7 and Virtex-6 HXT

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP 10-Gigabit Ethernet PCS/PMA core forms a seamless interface between the Xilinx@reg; 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems. The core supports 10GBASE-R on Virtex®-7, Kintex™-7, and Virtex-6 HXT FPGAs.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and Kintex™-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and a line rate of up to 10.3125 Gb/s on 1, 2, 4 or 8 lanes using GTX transceivers in Kintex™-7 and Virtex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The core supports sharing a GTX transceiver between a transmitter and receiver. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx® 10-Gigabit Ethernet Media Access Controller (MAC) and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.

This guide provides information about generating a LogiCORE™ IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.