XAUI
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XAUI
| Date | Name |
|---|---|
| 04/19/2010 | XAUI v9.2 Getting Started Guide(PDF, ver 2.2, 939 KB )
The LogiCORE™ IP XAUI Getting Started Guide provides instructions for generating the core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools. |
| 04/19/2010 | XAUI v9.2 Data Sheet (PDF, ver 2.2, 462 KB )
The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gbps Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA families. |
| 04/19/2010 | XAUI v9.2 User Guide(PDF, ver 3.2, 3.46 MB )
The XAUI v9.2 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools. |
| 03/01/2011 | LogiCORE XAUI v10.1 User Guide(PDF, ver 3.3, 4.13 MB )
The XAUI v10.1 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools. |
| 03/01/2011 | XAUI v10.1 Data Sheet (PDF, ver 2.3, 547 KB )
The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices. |
| 01/18/2012 | LogiCORE IP XAUI v10.2 Data Sheet(PDF, ver 2.4, 545 KB )
The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Xilinx® Virtex®-7, Kintex™-7, Virtex-6, Virtex-5, Virtex-4, and Spartan®-6 FPGA devices. |
| 01/18/2012 | LogiCORE XAUI v10.2 User Guide(PDF, ver 3.4, 3.54 MB )
The eXtended Attachment Unit Interface (XAUI) core is a fully-verified solution design that supports Verilog and VHSIC Hardware Description Language (VHDL). The example design in this guide is provided in both Verilog and VHDL. |
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