Telecommunications

This Release Notes and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Link Layer v7.2 Core (released in ISE Design Suite 12.1) and the v7.2 rev1 Core (released as a patch below), and contains the following information:

• New Features
• Bug Fixes
• General Information
• Known Issues

The Xilinx LogiCORE™ IP SPI-3 Link Layer core provides a complete, pre-engineered solution that is fully compatible with the OIF-SPI3-01.0 System Packet Interface Level-3 implementation agreement. This fully verified solution implements the SPI-3 Link Layer interface, which interconnects with SPI-3 Physical (PHY) Layer devices.

The SPI-3 Link Layer Getting Started Guide provides information about generating a LogiCORE™ IP SPI-3 Link Layer core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP SPI-4.2 Core v10.5 User Guide describes the function and operation of the Xilinx® SPI-4.2 (PL4) Core, and provides information about designing, customizing and implementing the core.

The Xilinx SPI-4.2 (PL4) core implements and is fully compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces.

The Xilinx SPI-4.2 (PL4) core implements and is compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces. This document contains information about the AXI4 version of the core.

This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v10.1 Core, released in ISE Design Suite 12.1 and contains the following information: 

• New Features 
• Bug Fixes 
• General Information 
• Known Issues 

The LogiCORE™ IP SPI-4.2 Core v9.3 User Guide describes the function and operation of the Xilinx® SPI-4.2 (PL4) Core, and provides information about designing, customizing and implementing the core.

The Xilinx SPI-4.2 (PL4) core implements and is fully compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces.

This user guide describes the function and operation of the Xilinx LogiCORE™ SPI-4.2 (PL4) core, and provides information about designing, customizing and implementing the core. This document contains information about the AXI4 version of the core.

This Release Note and Known Issues Answer Record is for the SPI-4.2 Lite (POS-PHY L4) v5.2 Core, released in ISE Design Suite 12.1, and contains the following information: 

• New Features 
• Bug Fixes 
• General Information 
• Known Issues 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: 
http://www.xilinx.com/support/documentation/userguides/xtp025.pdf

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the SPI-4.2 Core.

To communicate that Xilinx is modifying the offerings associated with these LogiCORE™ IP products.

The Xilinx SPI-4.2 (PL4) core implements and is compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces. This document contains information about the AXI4 version of the core.

This user guide describes the function and operation of the Xilinx LogiCORE™ SPI-4.2 (PL4) core, and provides information about designing, customizing and implementing the core. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx FPGA families.

The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx® FPGA families.

The LogiCORE™ IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and Kintex™-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and a line rate of up to 10.3125 Gb/s on 1, 2, 4 or 8 lanes using GTX transceivers in Kintex™-7 and Virtex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The core supports sharing a GTX transceiver between a transmitter and receiver. This document contains information about the AXI4 version of the core.

The 3GPP Mixed Mode Turbo Decoder LogiCORE™ provides a flexible turbo convolutional decode function for both LTE and WCDMA air interfaces. This document contains information about the AXI4 version of the core.