SPI-3 Link Layer Interface, Multi-channel

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Date	Name

11/17/2010	SPI-3 Link Layer v7.2 - Release Notes and Known Issues for ISE Design Suite 12.1 This Release Notes and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Link Layer v7.2 Core (released in ISE Design Suite 12.1) and the v7.2 rev1 Core (released as a patch below), and contains the following information: New Features Bug Fixes General Information Known Issues For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf Was this document helpful? Yes \| No
12/14/2010	LogiCORE IP SPI-3 Link Layer v7.3 Data Sheet(PDF, ver 8.0, 1.66 MB ) The Xilinx LogiCORE™ IP SPI-3 Link Layer core provides a complete, pre-engineered solution that is fully compatible with the OIF-SPI3-01.0 System Packet Interface Level-3 implementation agreement. This fully verified solution implements the SPI-3 Link Layer interface, which interconnects with SPI-3 Physical (PHY) Layer devices. Was this document helpful? Yes \| No
12/14/2010	LogiCORE IP SPI-3 Link Layer v7.3 Getting Started Guide(PDF, ver 6.0, 1.46 MB ) The SPI-3 Link Layer Getting Started Guide provides information about generating a LogiCORE™ IP SPI-3 Link Layer core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools. Was this document helpful? Yes \| No