SPI-4 Phase 2 Interface Solutions

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SPI-4 Phase 2 Interface Solutions

Date	Name

06/22/2011	LogiCORE IP SPI-4.2 v10.5 User Guide(PDF, ver 12.0, 4.88 MB ) The LogiCORE™ IP SPI-4.2 Core v10.5 User Guide describes the function and operation of the Xilinx® SPI-4.2 (PL4) Core, and provides information about designing, customizing and implementing the core. Was this document helpful? Yes \| No
06/22/2011	LogiCORE IP SPI-4.2 v10.5 Data Sheet(PDF, ver 11.0, 664 KB ) The Xilinx SPI-4.2 (PL4) core implements and is fully compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces. Was this document helpful? Yes \| No
03/01/2011	LogiCORE IP SPI-4.2 v11.1 Data Sheet (AXI)(PDF, ver 1.0, 766 KB ) The Xilinx SPI-4.2 (PL4) core implements and is compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
09/24/2010	SPI-4.2 v10.1 - Release Notes and Known Issues for ISE Design Suite 12.1 This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v10.1 Core, released in ISE Design Suite 12.1 and contains the following information: New Features Bug Fixes General Information Known Issues For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf Was this document helpful? Yes \| No
03/01/2011	LogiCORE IP SPI-4.2 v10.4 User Guide(PDF, ver 11.0, 4.88 MB ) The LogiCORE™ IP SPI-4.2 Core v9.3 User Guide describes the function and operation of the Xilinx® SPI-4.2 (PL4) Core, and provides information about designing, customizing and implementing the core. Was this document helpful? Yes \| No
03/01/2011	LogiCORE IP SPI-4.2 v10.4 Data Sheet(PDF, ver 10.0, 663 KB ) The Xilinx SPI-4.2 (PL4) core implements and is fully compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces. Was this document helpful? Yes \| No
03/01/2011	LogiCORE IP SPI-4.2 v11.1 User Guide (AXI)(PDF, ver 1.0, 4.41 MB ) This user guide describes the function and operation of the Xilinx LogiCORE™ SPI-4.2 (PL4) core, and provides information about designing, customizing and implementing the core. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
05/03/2010	SPI-4.2 Lite v5.2 - Release Notes and Known Issues for ISE Design Suite 12.1 This Release Note and Known Issues Answer Record is for the SPI-4.2 Lite (POS-PHY L4) v5.2 Core, released in ISE Design Suite 12.1, and contains the following information: New Features Bug Fixes General Information Known Issues For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/userguides/xtp025.pdf Was this document helpful? Yes \| No
11/23/2010	Design Advisory for the SPI-4.2 Core Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. This Design Advisory covers the SPI-4.2 Core. Was this document helpful? Yes \| No
04/19/2010	XCN10021 - Product Change Notice for Select LogiCORE Products(PDF, ver 1.0, 52 KB ) To communicate that Xilinx is modifying the offerings associated with these LogiCORE™ IP products. Was this document helpful? Yes \| No
10/19/2011	LogiCORE IP SPI-4.2 v11.2 Data Sheet (AXI)(PDF, ver 2.5, 809 KB ) The Xilinx SPI-4.2 (PL4) core implements and is compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. The core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products, which enables higher-level functions such as switches, bridges, and NPU interfaces. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
10/19/2011	LogiCORE IP SPI-4.2 v11.2 User Guide (AXI)(PDF, ver 2.5, 4.57 MB ) This user guide describes the function and operation of the Xilinx LogiCORE™ SPI-4.2 (PL4) core, and provides information about designing, customizing and implementing the core. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No

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