Wireless

This version of the Turbo Convolution Code (TCC) encoder is designed to meet the 3GPP LTE mobile communication system specification.

The Xilinx LogiCORE™ IP DUC/DDC Compiler implements high-performance, optimized Digital Up and Down-Converter modules for use in wireless base stations and other suitable applications. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP LTE Uplink Channel Decoder implements an AXI4 compliant, high-performance, optimized decoder block for the 3GPP TS 36.212 v9.3.0 Uplink Shared Channel (UL-SCH). This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP LTE Physical Uplink Control Channel (PUCCH) Receiver implements an AXI4-Stream compliant, high-performance, optimized block for the 3GPP TS 36.211 v9.00 Physical uplink control channel. This document contains information about the AXI4 version of the core.

The LogiCORE IP LTE Fast Fourier Transform (FFT) implements all transform lengths required by the 3GPP LTE specification, including the 1536-point transform for 15 MHz bandwidth support.

The Xilinx LogiCORE™ IP 3GPP LTE Channel Estimator v1.0 implements AXI4-Stream compliant, channel estimation functionality suitable to support decoding of the Physical Uplink Shared Channel (PUSCH) in LTE eNodeB applications as defined in the 3GPP TS 36.211 specification. This document contains information about the AXI4 version of the core.

Pre-distortion negates the non-linear effects of a power amplifier (PA) generated when transmitting a wide-band signal. Pre-distortion allows a PA to achieve greater efficiency by operating at higher output power while still maintaining spectral compliance, reducing system capital and operational expenditure. The solution is targeted for base stations used in third and fourth generation (3G/4G) mobile technologies and beyond.

The Xilinx® 3GPP LTE MIMO Encoder v2.0 core implements multiple-input, multiple-output (MIMO) encoding for LTE eNodeB applications as defined in the 3GPP TS 36.211 v.8.7 specification.

Crest Factor Reduction (CFR) is used to limit the dynamic range of the signals being transmitted in Wireless Communications and other applications. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP LTE MIMO Decoder implements the uplink MIMO decoding functions for applications following the 3rd Generation Partnership Projects (3GPP); Evolved Universal Radio Access (E-UTRA); Physical Channels and Modulation (Release 9), 3GPP TS 36.211 V9.0.0 (2009-12) specification. This document contains information about the AXI4 version of the core.

The Xilinx® LTE RACH detector core decodes P-RACH data encoded according to the 3GPP TS 36.211 v9.0 (2009-12) Physical Channels and Modulation specification.

The LogiCORE™ IP Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

The LogiCORE™ IP CPRI core is a high-performance, low-cost flexible solution that implements the Common Packet Radio Interface (CPRI).

The Xilinx® LogiCORE™ IP Discrete Fourier Transform (DFT) core meets the requirements for 3GPP Long Term Evolution (LTE) systems.

This is the Data Sheet for the 3GPP RACH Preamble Detector v1.0 core.

The Xilinx LogiCORE™ IP DUC/DDC Compiler implements high-performance, optimized Digital Up and Down-Converter modules for use in wireless base stations and other suitable applications.

This is the data sheet for the 3GPP Searcher v1.0 core

This is the data sheet for the 3GPP Searcher v1.0 core

The LogiCORE™ IP CPRI core is a high-performance, low-cost flexible solution that implements the Common Packet Radio Interface (CPRI).

This user guide provides information about generating a LogiCORE™ IP LTE RACH Detector core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 Mbps, 1.5 Gbps, and 3 Gbps line rates using GTP or GTX transceivers in Virtex®-5, Spartan®-6 and Virtex-6 FPGAs. 6 Gbps line rate is supported in Virtex-6 devices. The OBSAI core can be configured as a master or slave for use in base station or Remote RF Units (RRUs).

Crest Factor Reduction (CFR) is used to limit the dynamic range of the signals being transmitted in Wireless Communications and other applications.

The Xilinx® LTE UL Channel Decoder core provides designers with an LTE Uplink Channel Decoding block for the 3GPP TS 36.212 v8.5.0 Multiplexing and Channel Coding specification.

This is the Data Sheet for the 3GPP RACH Preamble Detector v1.0 core

Pre-distortion negates the non-linear effects of a power amplifier (PA) generated when transmitting a wide-band signal. Pre-distortion allows a PA to achieve greater efficiency by operating at higher output power while still maintaining spectral compliance, reducing system capital and operational expenditure.

The Xilinx LogiCORE™ IP LTE MIMO Decoder v1.0 implements the uplink MIMO decoding functions for applications following the "3rd Generation Partnership Projects (3GPP); Evolved Universal Radio Access (EUTRA); Physical Channels and Modulation (Release 8), 3GPP TS 36.211 V8.5.0 (2008-05)" specification.

This user guide provides information about the Xilinx® LogiCORE™ IP 3GPP LTE Turbo Encoder v2.0 bit accurate C model for 32- and 64-bit Linux and 32- and 64-bit Windows platforms.

To communicate that Xilinx is discontinuing certain Development Systems products.

The LogiCORE™ IP OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 Mb/s, 1.5 Gb/s, and 3 Gb/s line rates using GTP or GTX transceivers in Virtex®-5, Spartan®-6 and Virtex-6 FPGAs. 6 Gb/s line rate is supported in Virtex-6 devices. The OBSAI core can be configured as a master or slave for use in base station or Remote RF Units (RRUs). This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP 3GPP LTE Channel Estimator implements AXI4-Stream compliant, channel estimation functionality suitable to support decoding of the Physical Uplink Shared Channel (PUSCH) in LTE eNodeB applications as defined in the 3GPP TS 36.211 specification. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and Kintex™-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. This document contains information about the AXI4 version of the core.

This is the data sheet for the 3GPP Downlink Chip Rate v1.0 core.

This is the Product Brief for the 3GPP Downlink Chip Rate v1.0 core.

The Xilinx LogiCORE™ IP LTE DL Channel Encoder core provides designers with an LTE Downlink Channel Encoding block for the 3GPP TS 36.212 v9.0.0 Multiplexing and Channel Coding specification.

The Xilinx® 3GPP LTE MIMO Encoder v3.0 core implements multiple-input, multiple-output (MIMO) encoding for LTE eNodeB applications as defined in the 3GPP TS 36.211 v.9.1 specification. It represents one IP component in the Xilinx broader LTE Baseband Platform. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Common Packet Radio Interface (CPRI™) core is a high-performance, low-cost flexible solution for implementation of the CPRI interface. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Open Base Station Architecture Initiative (OBSAI) core implements an OBSAI RP3 interface supporting RP3-01 at various line rates. The OBSAI core can be configured as a master or slave for use in base station or Remote RF Units (RRUs). This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and a line rate of up to 10.3125 Gb/s on 1, 2, 4 or 8 lanes using GTX transceivers in Kintex™-7 and Virtex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The core supports sharing a GTX transceiver between a transmitter and receiver. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP CPRI core is a high-performance, low-cost flexible solution that implements the Common Packet Radio Interface (CPRI).

The LogiCORE™ IP CPRI core is a high-performance, low-cost flexible solution that implements the Common Packet Radio Interface (CPRI).

The LogiCORE™ IP Common Packet Radio Interface (CPRI™) core is a high-performance, low-cost flexible solution for implementation of the CPRI interface. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Discrete Fourier Transform (DFT) core meets the requirements for 3GPP Long Term Evolution (LTE) systems.

The LogiCORE™ IP OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 Mbps, 1.5 Gbps, and 3 Gbps line rates using GTP or GTX transceivers in Virtex®-5, Spartan®-6 and Virtex-6 FPGAs. 6 Gbps line rate is supported in Virtex-6 devices. The OBSAI core can be configured as a master or slave for use in base station or Remote RF Units (RRUs).

The LogiCORE™ IP OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 Mb/s, 1.5 Gb/s, and 3 Gb/s line rates using GTP or GTX transceivers in Virtex®-5, Spartan®-6 and Virtex-6 FPGAs. 6 Gb/s line rate is supported in Virtex-6 devices. The OBSAI core can be configured as a master or slave for use in base station or Remote RF Units (RRUs). This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Open Base Station Architecture Initiative (OBSAI) core implements an OBSAI RP3 interface supporting RP3-01 at various line rates. The OBSAI core can be configured as a master or slave for use in base station or Remote RF Units (RRUs). This document contains information about the AXI4 version of the core.

This is the Data Sheet for the 3GPP RACH Preamble Detector v1.0 core.

This is the Data Sheet for the 3GPP RACH Preamble Detector v1.0 core

To communicate that Xilinx is discontinuing certain Development Systems products.

This is the data sheet for the 3GPP Downlink Chip Rate v1.0 core.

This is the Product Brief for the 3GPP Downlink Chip Rate v1.0 core.

This is the data sheet for the 3GPP Searcher v1.0 core

This is the data sheet for the 3GPP Searcher v1.0 core

The LogiCORE™ IP Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

The 3GPP LTE Turbo Encoder v1.0 core has a bit accurate C model designed for system modeling. This allows the user to model the core performance.

This user guide provides information about the Xilinx® LogiCORE™ IP 3GPP LTE Turbo Encoder v2.0 bit accurate C model for 32- and 64-bit Linux and 32- and 64-bit Windows platforms.

This version of the Turbo Convolution Code (TCC) encoder is designed to meet the 3GPP LTE mobile communication system specification.

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE IP DL Channel Encoder Core. 

The following information is listed for each version of the core: 

• New Features 
• Resolved Issues
• Known Issues

The Xilinx LogiCORE™ IP LTE DL Channel Encoder core provides designers with an LTE Downlink Channel Encoding block for the 3GPP TS 36.212 v9.0.0 Multiplexing and Channel Coding specification.

The Xilinx® LTE UL Channel Decoder core provides designers with an LTE Uplink Channel Decoding block for the 3GPP TS 36.212 v8.5.0 Multiplexing and Channel Coding specification.

The Xilinx® LogiCORE™ IP LTE Uplink Channel Decoder implements an AXI4 compliant, high-performance, optimized decoder block for the 3GPP TS 36.212 v9.3.0 Uplink Shared Channel (UL-SCH). This document contains information about the AXI4 version of the core.

The Xilinx® 3GPP LTE MIMO Encoder v2.0 core implements multiple-input, multiple-output (MIMO) encoding for LTE eNodeB applications as defined in the 3GPP TS 36.211 v.8.7 specification.

The Xilinx® 3GPP LTE MIMO Encoder v3.0 core implements multiple-input, multiple-output (MIMO) encoding for LTE eNodeB applications as defined in the 3GPP TS 36.211 v.9.1 specification. It represents one IP component in the Xilinx broader LTE Baseband Platform. This document contains information about the AXI4 version of the core.

Crest Factor Reduction (CFR) is used to limit the dynamic range of the signals being transmitted in Wireless Communications and other applications.

Crest Factor Reduction (CFR) is used to limit the dynamic range of the signals being transmitted in Wireless Communications and other applications. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP LTE MIMO Decoder v1.0 implements the uplink MIMO decoding functions for applications following the "3rd Generation Partnership Projects (3GPP); Evolved Universal Radio Access (EUTRA); Physical Channels and Modulation (Release 8), 3GPP TS 36.211 V8.5.0 (2008-05)" specification.

The Xilinx® LogiCORE™ IP LTE MIMO Decoder implements the uplink MIMO decoding functions for applications following the 3rd Generation Partnership Projects (3GPP); Evolved Universal Radio Access (E-UTRA); Physical Channels and Modulation (Release 9), 3GPP TS 36.211 V9.0.0 (2009-12) specification. This document contains information about the AXI4 version of the core.

This user guide provides information about generating a LogiCORE™ IP LTE RACH Detector core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The Xilinx® LTE RACH detector core decodes P-RACH data encoded according to the 3GPP TS 36.211 v9.0 (2009-12) Physical Channels and Modulation specification.

Design Advisory for the DUC/DDC Compiler.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

The Xilinx LogiCORE™ IP DUC/DDC Compiler implements high-performance, optimized Digital Up and Down-Converter modules for use in wireless base stations and other suitable applications.

The Xilinx LogiCORE™ IP DUC/DDC Compiler implements high-performance, optimized Digital Up and Down-Converter modules for use in wireless base stations and other suitable applications. This document contains information about the AXI4 version of the core.

The LogiCORE IP LTE Fast Fourier Transform (FFT) implements all transform lengths required by the 3GPP LTE specification, including the 1536-point transform for 15 MHz bandwidth support.

The Xilinx LogiCORE™ IP 3GPP LTE Channel Estimator v1.0 implements AXI4-Stream compliant, channel estimation functionality suitable to support decoding of the Physical Uplink Shared Channel (PUSCH) in LTE eNodeB applications as defined in the 3GPP TS 36.211 specification. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ IP 3GPP LTE Channel Estimator implements AXI4-Stream compliant, channel estimation functionality suitable to support decoding of the Physical Uplink Shared Channel (PUSCH) in LTE eNodeB applications as defined in the 3GPP TS 36.211 specification. This document contains information about the AXI4 version of the core.

Pre-distortion negates the non-linear effects of a power amplifier (PA) generated when transmitting a wide-band signal. Pre-distortion allows a PA to achieve greater efficiency by operating at higher output power while still maintaining spectral compliance, reducing system capital and operational expenditure. The solution is targeted for base stations used in third and fourth generation (3G/4G) mobile technologies and beyond.

Pre-distortion negates the non-linear effects of a power amplifier (PA) generated when transmitting a wide-band signal. Pre-distortion allows a PA to achieve greater efficiency by operating at higher output power while still maintaining spectral compliance, reducing system capital and operational expenditure.

The Xilinx® LogiCORE™ IP LTE Physical Uplink Control Channel (PUCCH) Receiver implements an AXI4-Stream compliant, high-performance, optimized block for the 3GPP TS 36.211 v9.00 Physical uplink control channel. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and Kintex™-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex®-6 and a line rate of up to 10.3125 Gb/s on 1, 2, 4 or 8 lanes using GTX transceivers in Kintex™-7 and Virtex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The core supports sharing a GTX transceiver between a transmitter and receiver. This document contains information about the AXI4 version of the core.