Error Correction

The LogiCORE™ IP Viterbi Decoder User Guide provides information about generating a Viterbi decoder core and customizing and simulating the core using provided examples. It also includes advice on designing with the core and troubleshooting tips.

Design File(s):

• ug745.zip

This is the data sheet for the 802.16e CTC Encoder v3.0 core

This is the product brief for the IEEE 802.16e CTC Decoder v4.0 core

The Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.

The Convolution Encoder core can be used in a wide variety of error correcting applications and is typically used in conjunction with the Viterbi Decoder (DS247).

The LogiCORE™ IP Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

The LogiCORE™ Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on. The core meets the requirements of most standards that employ RS codes, such as CCSDS, DVB, ETSI-BRAN, IEEE802.16, G.709, IESS-308. This document contains information about the AXI4 version of the core.

The Xilinx® DVB-S.2 FEC Encoder core provides designers with a Forward Error Correction (FEC) Encoding block for DVB-S.2 systems.

The Xilinx LogiCORE™ IP LTE DL Channel Encoder core provides designers with an LTE Downlink Channel Encoding block for the 3GPP TS 36.212 v9.0.0 Multiplexing and Channel Coding specification.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems such as communications systems and disk drives where data is transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

Convolution encoding is used to encode data prior to transmission over a channel. The received data is decoded by the classic Viterbi decoder. This document contains information about the AXI4 version of the core.

The Convolution Encoder core can be used in a wide variety of error correcting applications and is typically used in conjunction with the Viterbi Decoder (DS247).

Convolution encoding is used to encode data prior to transmission over a channel. The received data is decoded by the classic Viterbi decoder. This document contains information about the AXI4 version of the core.

This data sheet is restricted to official use only.

This data sheet is restricted to official use only.

This is the data sheet for Additive White Gaussian Noise (AWGN) Core

This is the product brief for the IEEE 802.16e CTC Decoder v4.0 core

This is the data sheet for the 802.16e CTC Encoder v3.0 core

To communicate that Xilinx is discontinuing certain Development Systems products.

The Xilinx® DVB-S.2 FEC Encoder core provides designers with a Forward Error Correction (FEC) Encoding block for DVB-S.2 systems.

The Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The LogiCORE™ Reed-Solomon decoder (with the Reed-Solomon algorithm) is used for Forward Error Correction (FEC) in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on. The core meets the requirements of most standards that employ RS codes, such as CCSDS, DVB, ETSI-BRAN, IEEE802.16, G.709, IESS-308. This document contains information about the AXI4 version of the core.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception, for example, communications systems, disk drives, and so on.

The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems such as communications systems and disk drives where data is transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

This core performs decoding for the turbo product codes listed in the IEEE 802.16 and 802.16a standards.

This core performs TPC encoding as defined in the IEEE 802.16 and 802.16a standards.

The LogiCORE™ IP Viterbi Decoder User Guide provides information about generating a Viterbi decoder core and customizing and simulating the core using provided examples. It also includes advice on designing with the core and troubleshooting tips.

Design File(s):

• ug745.zip

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.

The Viterbi Decoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Turbo Convolution Code (TCC) decoder core is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels, and is designed to meet the 3GPP Mobile Communication System specification.

The 3GPP LTE Turbo Encoder v1.0 core has a bit accurate C model designed for system modeling. This allows the user to model the core performance.