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| Date | Name |
|---|---|
| 03/01/2011 | CIC Compiler v2.0 Data Sheet(PDF, ver 2.1, 899 KB )
The CIC Compiler core provides the ability to design and implement Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx® FPGA devices. |
| 06/22/2011 | LogiCORE IP CIC Compiler v3.0 Data Sheet (AXI)(PDF, ver 1.0, 1.2 MB )
The Xilinx® LogiCORE™ IP CIC Compiler core provides the ability to design and implement AXI4-Stream-compliant Cascaded Integrator-Comb (CIC) filters. This document contains information about the AXI4 version of the core. |
| 06/20/2011 | LogiCORE IP Cascaded Integrator Comb Compiler (CIC Compiler) - Release Notes and Known Issues
For installation instructions for IP Update 1 and design tools requirements, see (Xilinx Answer 29185). |
| Date | Name |
|---|---|
| 03/01/2011 | LogiCORE IP FIR Compiler v5.0 Data Sheet(PDF, ver 5.1, 2.08 MB )
The Xilinx® LogiCORE™ IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters utilizing either Multiply-Accumulate (MAC) or Distributed Arithmetic (DA) architectures. |
| 03/01/2011 | LogiCORE IP FIR Compiler v6.2 Data Sheet (AXI)(PDF, ver 1.2, 1.63 MB )
The Xilinx LogiCORE™ IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters. This document contains information about the AXI4 version of the core. |
| 10/19/2011 | LogiCORE IP FIR Compiler v6.3 Data Sheet (AXI)(PDF, ver 1.3, 1.93 MB )
The Xilinx LogiCORE™ IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters. This document contains information about the AXI4 version of the core. |
| 04/24/2012 | LogiCORE IP FIR Compiler v6.3 Bit Accurate C Model User Guide(PDF, ver 1.2, 634 KB )
The Xilinx® LogiCORE™ IP FIR Compiler v6.3 core bit accurate C model is a self-contained, linkable, shared library that models the functionality of this core with finite precision arithmetic. This model provides a bit accurate representation of the various modes of the FIR Compiler v6.3 core, and it is suitable for inclusion in a larger framework for system-level simulation or core-specific verification. |