CoreConnect

The Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI transactions into PLBv46 transactions. It functions as 32/64-bit slave on AXI4 and 32/64-bit master on the PLB. This document contains information about the AXI4 version of the core.

This is the data sheet for the PLBV46 Master Single (v1.00a) core

The Processor Local Bus (PLB v4.6) to AMBA@reg; (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. This document contains information about the AXI4 version of the core.

The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers.

The PLBv46 (Processor Local Bus Version 4.6 with Xilinx simplification) to PLBv46 Bridge allows the designer to connect two PLB buses. The PLBv46 to PLBv46 Bridge can be used to isolate the slow PLB peripherals from the primary PLB and improve the system performance.

This is the data sheet for the PLBV46 to OPB Bridge (v1.00a) core

This is the data sheet for the On-Chip Peripheral Bus V2.0 with OPB Arbiter (v1.10d) core

The Utility Bus Split core splits a bus into smaller buses using the Xilinx Platform Studio (XPS). The core splits one input bus into two output buses which serve as glue logic between peripherals.

The Fabric Co-processor Bus (FCB) connects one or more FPGA fabric accelerator slaves to the Auxiliary Processor Unit (APU) controller in a Virtex®-4 PowerPC® 405.

The FCB to FSL Bridge combines the power of the Virtex®-4 PowerPC™ APU controller with the ease of use of the Fast Simplex Link (FSL) protocol. The core connects FSL interfaced coprocessor cores to the PowerPC 405 via the Fabric Co-processor Bus (FCB) making it easy to extend the PowerPC processing unit with application specific functions.

This is a data sheet for Processor Local Bus (PLB) Arbiter.

This is the data sheet for the PLBV46 Master (v1.00a) core

This is the data sheet for the OPB to DCR Bridge (v1.00b) core

The Xilinx® Multi-Channel (MCH) and PLBv46 Slave Burst (MCH_PLBv46_Slave_Burst) provides a bi-directional interface between a parameterizable number of channel interfaces and an PLBv46 Slave Burst interface to an IP core.

The PLB to FSL Bridge can be used to provide FSL interface connection to any PLB v4.6 master. Both FSL master and slave interfaces are available for bi-directional transfer of data.

The Fabric Co-processor Bus for PPC440 (FCB_V20) connects one or more FPGA fabric accelerator slaves to the Auxiliary Processor Unit (APU) controller in a Virtex®-5 FX PowerPC® 440

The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE products. It provides a bi-directional interface between a User IP core and the PLB v4.6 bus standard. This version of the PLBV46 Master Burst has been designed for PLBV46 Master operations consisting of single data beat read or write transfers and Fixed Length Burst Transfers of 2 to 16 data beats.

The On-Chip Peripheral Bus (OPB) to Processor Local Bus (PLB v4.6) Bridge module translates OPB transactions into PLBV46 transactions. It functions as a slave on the OPB side and a master on the PLBV46 side.

This is the data sheet for Processor Local Bus (PLB) v3.4.

This is the data sheet for the PLBV46 to DCR Bridge (v1.00a) core

The AMBA® (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4 transactions into AHB-Lite transactions. It functions as a slave on the AXI4 interface and as a master on the AHB-Lite interface. The AXI to AHB-Lite Bridge main use model is to connect the AHB-Lite slaves with AXI masters. This document contains information about the AXI4 version of the core.

The PLBv46 Slave Burst core is a part of the Xilinx family of PLB v4.6 compatible products. It provides a bi-directional interface between a User IP core and the PLB v4.6 bus standard.

The Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI transactions into PLBv46 transactions. It functions as 32/64-bit slave on AXI4 and 32/64-bit master on the PLB. This document contains information about the AXI4 version of the core.

The Processor Local Bus (PLB v4.6) to AMBA® (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. It functions as a slave on the PLBV46 and as a master on the AXI4. The PLBV46 to AXI Bridge main use model is to connect the AXI slaves with PLB masters. This document contains information about the AXI4 version of the core.

This is the data sheet for the Device Control Register Bus (DCR) v2.9 core.

The PLBv46 (Processor Local Bus Version 4.6 with Xilinx simplification) to PLBv46 Bridge allows the designer to connect two PLB buses. The PLBv46 to PLBv46 Bridge can be used to isolate the slow PLB peripherals from the primary PLB and improve the system performance.

The Xilinx® 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system.

The AXI Quad Serial Peripheral Interface (AXI Quad SPI) connects the Advanced eXtensible Interface (AXI4) to those SPI slave devices which are supporting the Dual or Quad SPI protocol along with Standard SPI protocol instruction set. This document contains information about the AXI4 version of the core.

This is the data sheet for the OPB to OPB Bridge (Lite Version) (v1.00a) core

The AMBA® (Advanced Microcontroller Bus Architecture) AHB-Lite (Advanced High Performance Bus) to AXI (Advanced extensible interface) bridge translates AHB-Lite transactions into AXI4 transactions. It functions as an AHB-Lite slave on the AHB bus and as an AXI master on the AXI bus. This document contains information about the AXI4 version of the core.

The Processor Local Bus (PLB v4.6) to AMBA® (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. It functions as a slave on the PLBV46 and as a master on the AXI4. The PLBV46 to AXI Bridge main use model is to connect the AXI slaves with PLB masters. This document contains information about the AXI4 version of the core.

The Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI transactions into PLBv46 transactions. It functions as 32/64-bit slave on AXI4 and 32/64-bit master on the PLB. This document contains information about the AXI4 version of the core.

The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad SPI protocol instruction set. This core provides a serial interface to SPI slave devices such as SPI serial flash from Winbond and Numonyx. This document contains information about the AXI4 version of the core.

This is the data sheet for the Device Control Register Bus (DCR) v2.9 core.

This is the data sheet for the OPB Arbiter (v1.02e) core

This is the data sheet for the On-Chip Peripheral Bus V2.0 with OPB Arbiter (v1.10d) core

This is the data sheet for the OPB IPIF (v3.01c) core

This is the data sheet for the OPB to DCR Bridge (v1.00b) core

This is the data sheet for the OPB to OPB Bridge (Lite Version) (v1.00a) core

The Xilinx® 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system.

The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers.

The PLBv46 Slave Burst core is a part of the Xilinx family of PLB v4.6 compatible products. It provides a bi-directional interface between a User IP core and the PLB v4.6 bus standard.

This is a data sheet for Processor Local Bus (PLB) Arbiter.

The On-Chip Peripheral Bus (OPB) to Processor Local Bus (PLB v4.6) Bridge module translates OPB transactions into PLBV46 transactions. It functions as a slave on the OPB side and a master on the PLBV46 side.

This is the data sheet for the PLB IPIF (v2.02a) core

This is the data sheet for Processor Local Bus (PLB) v3.4.

The Utility Bus Split core splits a bus into smaller buses using the Xilinx Platform Studio (XPS). The core splits one input bus into two output buses which serve as glue logic between peripherals.

The FCB to FSL Bridge combines the power of the Virtex®-4 PowerPC™ APU controller with the ease of use of the Fast Simplex Link (FSL) protocol. The core connects FSL interfaced coprocessor cores to the PowerPC 405 via the Fabric Co-processor Bus (FCB) making it easy to extend the PowerPC processing unit with application specific functions.

The PLBv46 (Processor Local Bus Version 4.6 with Xilinx simplification) to PLBv46 Bridge allows the designer to connect two PLB buses. The PLBv46 to PLBv46 Bridge can be used to isolate the slow PLB peripherals from the primary PLB and improve the system performance.

The PLBv46 (Processor Local Bus Version 4.6 with Xilinx simplification) to PLBv46 Bridge allows the designer to connect two PLB buses. The PLBv46 to PLBv46 Bridge can be used to isolate the slow PLB peripherals from the primary PLB and improve the system performance.

This is the data sheet for the PLBV46 to DCR Bridge (v1.00a) core

This is the data sheet for the PLBV46 to OPB Bridge (v1.00a) core

The PLB to FSL Bridge can be used to provide FSL interface connection to any PLB v4.6 master. Both FSL master and slave interfaces are available for bi-directional transfer of data.

This is the data sheet for the PLBV46 Master (v1.00a) core

This is the data sheet for the PLBV46 Master Single (v1.00a) core

The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE products. It provides a bi-directional interface between a User IP core and the PLB v4.6 bus standard. This version of the PLBV46 Master Burst has been designed for PLBV46 Master operations consisting of single data beat read or write transfers and Fixed Length Burst Transfers of 2 to 16 data beats.

The Xilinx® Multi-Channel (MCH) and PLBv46 Slave Burst (MCH_PLBv46_Slave_Burst) provides a bi-directional interface between a parameterizable number of channel interfaces and an PLBv46 Slave Burst interface to an IP core.

The Fabric Co-processor Bus (FCB) connects one or more FPGA fabric accelerator slaves to the Auxiliary Processor Unit (APU) controller in a Virtex®-4 PowerPC® 405.

The Fabric Co-processor Bus for PPC440 (FCB_V20) connects one or more FPGA fabric accelerator slaves to the Auxiliary Processor Unit (APU) controller in a Virtex®-5 FX PowerPC® 440

The Processor Local Bus (PLB v4.6) to AMBA@reg; (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. This document contains information about the AXI4 version of the core.

The Processor Local Bus (PLB v4.6) to AMBA® (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. It functions as a slave on the PLBV46 and as a master on the AXI4. The PLBV46 to AXI Bridge main use model is to connect the AXI slaves with PLB masters. This document contains information about the AXI4 version of the core.

The Processor Local Bus (PLB v4.6) to AMBA® (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. It functions as a slave on the PLBV46 and as a master on the AXI4. The PLBV46 to AXI Bridge main use model is to connect the AXI slaves with PLB masters. This document contains information about the AXI4 version of the core.

The Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI transactions into PLBv46 transactions. It functions as 32/64-bit slave on AXI4 and 32/64-bit master on the PLB. This document contains information about the AXI4 version of the core.

The Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI transactions into PLBv46 transactions. It functions as 32/64-bit slave on AXI4 and 32/64-bit master on the PLB. This document contains information about the AXI4 version of the core.

The Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI transactions into PLBv46 transactions. It functions as 32/64-bit slave on AXI4 and 32/64-bit master on the PLB. This document contains information about the AXI4 version of the core.

The AMBA® (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4 transactions into AHB-Lite transactions. It functions as a slave on the AXI4 interface and as a master on the AHB-Lite interface. The AXI to AHB-Lite Bridge main use model is to connect the AHB-Lite slaves with AXI masters. This document contains information about the AXI4 version of the core.

The AMBA® (Advanced Microcontroller Bus Architecture) AHB-Lite (Advanced High Performance Bus) to AXI (Advanced extensible interface) bridge translates AHB-Lite transactions into AXI4 transactions. It functions as an AHB-Lite slave on the AHB bus and as an AXI master on the AXI bus. This document contains information about the AXI4 version of the core.

The AXI Quad Serial Peripheral Interface (AXI Quad SPI) connects the Advanced eXtensible Interface (AXI4) to those SPI slave devices which are supporting the Dual or Quad SPI protocol along with Standard SPI protocol instruction set. This document contains information about the AXI4 version of the core.

The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad SPI protocol instruction set. This core provides a serial interface to SPI slave devices such as SPI serial flash from Winbond and Numonyx. This document contains information about the AXI4 version of the core.