Debug and Trace

The AXI BFMs enable Xilinx customers to verify and simulate communication with AXI-based IP that is being developed.

Design File(s):

• axi_bfm_ug_examples.tar.gz

This is the data sheet for the MicroBlaze™ Debug Module (MDM) (v2.00a) core.

The BFM Synchronization Bus is a simple bus that connects the various Bus Functional Models in a design and allows communication between them.

The PLBv46 Monitor Bus Functional Model is a simulation hardware component that connects to a PLBv46 bus and continously samples the bus signals.

The CoreConnect Toolkit OPB Monitor Bus Functional Model is a simulation hardware component that connects to the OPB and continuously samples the bus signals.

The Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in real time.

The ChipScope™ PLB IBA core is a specialized Bus Analyzer core designed to debug embedded systems that contain the IBM CoreConnect Processor Local Bus (PLB).

The ChipScope™ ICON core provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the ChipScope Pro cores.

The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-5 GTP is a customizable core that can be used to evaluate and monitor the health of Virtex-5 GTP Transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the MGTs.

The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-6 GTX transceivers is a customizable core that can be used to evaluate and monitor the health of Virtex-6 GTX Transceivers.

The CoreConnect Toolkit PLB Slave Bus Functional Model is a simulation hardware component that has a PLB bus interface and may act as a bus slave.

The ChipScope™ Pro Integrated Logic Analyzer (ILA) core is a customizable logic analyzer core that can be used to monitor any internal signal of your design. The ILA core includes many advanced features of modern logic analyzers, including boolean trigger equations, trigger sequences, and storage qualification.

The CoreConnect Toolkit OPB Device Bus Functional Model is a simulation hardware component that has an OPB bus interface and may act as a master, as a slave, or as both.

The PLBv46 Master Bus Functional Model is a simulation hardware component that has a PLBv46 bus interface and may act as a bus master.

The CoreConnect Toolkit PLB Master Bus Functional Model is a simulation hardware component that has a PLB bus interface and may act as a bus master.

The ChipScope™ PLB Integrated Bus Analyzer (IBA) core is a specialized bus analyzer core designed to debug embedded systems that contain the IBM CoreConnect™ Processor Local Bus (PLB) version 4.6.

The PLBv46 Slave Bus Functional Model is a simulation hardware component that has a PLBv46 bus interface and may act as a bus slave.

The CoreConnect Toolkit PLB Monitor Bus Functional Model is a simulation hardware component that connects to a PLB bus and continously samples the bus signals.

The Agilent Trace Core 2 (ATC2) is a customizable debug capture core that is specially designed to work with the latest generation logic analyzers from Agilent Technologies. The ATC2 core provides external Agilent logic analyzers access to internal FPGA design nets.

The ChipScope™ OPB IBA core is a specialized Bus Analyzer core designed to debug embedded systems containing the IBM CoreConnect On-Chip Peripheral Bus (OPB).

The ChipScope™ Pro Integrated Bit Error Radio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that can be used to evaluate and monitor the health of Kintex-7 FPGA GTX transceivers.

The Agilent Trace Core 2 (ATC2) is a customizable debug capture core that is specially designed to work with the latest generation logic analyzers from Agilent Technologies. The ATC2 core provides external Agilent logic analyzers access to internal FPGA design nets.

The LogiCORE™ IP ChipScope™ Pro Integrated CONtroller core (ICON) provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the ChipScope Pro cores.

The Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in real time.

The ChipScope™ AXI Monitor core was designed to monitor and debug AXI interfaces. The core allows probing any signals going from a peripheral to the AXI interconnect. For instance, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor. This document contains information about the AXI4 version of the core.

The ChipScope™ AXI Monitor core was designed to monitor and debug AXI interfaces. The core allows probing any signals going from a peripheral to the AXI interconnect. For instance, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor. This document contains information about the AXI4 version of the core.

The ChipScope™ AXI Monitor core was designed to monitor and debug AXI interfaces. The core allows probing any signals going from a peripheral to the AXI interconnect. For instance, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor. This document contains information about the AXI4 version of the core.

The ChipScope™ Pro Integrated Logic Analyzer (ILA) core is a customizable logic analyzer core that can be used to monitor any internal signal of your design. The ILA core includes many advanced features of modern logic analyzers, including boolean trigger equations, trigger sequences, and storage qualification.

This document provides the design specification for the MicroBlaze™ Debug Module (MDM) which enables JTAG-based debugging of one or more MicroBlaze processors. This document contains information about the AXI4 version of the core.

The ChipScope™ Pro IBERT core for Kintex™-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Kintex-7 FPGA GTX transceivers.

The Xilinx® ChipScope™ Pro IBERT core for Spartan®-6 GTP transceivers is customizable and can be used to evaluate and monitor Spartan-6 GTP transceivers.

The ChipScope™ Pro IBERT core for Virtex®-5 FPGA GTX transceivers is a customizable core that can be used to evaluate and monitor Virtex-5 FPGA GTX transceivers.

The Xilinx ChipScope™ Pro IBERT core for Virtex®-6 FPGA GTH transceivers is customizable and can be used to evaluate and monitor the GTH transceivers. The design includes pattern generators and checkers implemented in FPGA logic, and access to the ports and DRP attributes of the serial transceivers.

The ChipScope™ Pro IBERT core for Virtex®-6 GTX transceivers can be used to evaluate and monitor GTX transceivers. The design includes pattern generators and checkers implemented in FPGA logic, and access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers.

The ChipScope™ Pro IBERT core for Virtex™-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Virtex-7 FPGA GTX tranceivers.

This is the data sheet for the MicroBlaze™ Debug Module (MDM) (v2.00a) core.

This document provides the design specification for the MicroBlaze™ Debug Module (MDM) which enables JTAG-based debugging of one or more MicroBlaze processors. This document contains information about the AXI4 version of the core.

The ChipScope™ OPB IBA core is a specialized Bus Analyzer core designed to debug embedded systems containing the IBM CoreConnect On-Chip Peripheral Bus (OPB).

The ChipScope™ Pro Integrated Logic Analyzer (ILA) core is a customizable logic analyzer core that can be used to monitor any internal signal of your design. The ILA core includes many advanced features of modern logic analyzers, including boolean trigger equations, trigger sequences, and storage qualification.

The ChipScope™ Pro Integrated Logic Analyzer (ILA) core is a customizable logic analyzer core that can be used to monitor any internal signal of your design. The ILA core includes many advanced features of modern logic analyzers, including boolean trigger equations, trigger sequences, and storage qualification.

The ChipScope™ PLB IBA core is a specialized Bus Analyzer core designed to debug embedded systems that contain the IBM CoreConnect Processor Local Bus (PLB).

The ChipScope™ PLB Integrated Bus Analyzer (IBA) core is a specialized bus analyzer core designed to debug embedded systems that contain the IBM CoreConnect™ Processor Local Bus (PLB) version 4.6.

The LogiCORE™ IP ChipScope™ Pro Integrated CONtroller core (ICON) provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the ChipScope Pro cores.

The ChipScope™ ICON core provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the ChipScope Pro cores.

The Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in real time.

The Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in real time.

The PLBv46 Slave Bus Functional Model is a simulation hardware component that has a PLBv46 bus interface and may act as a bus slave.

The PLBv46 Monitor Bus Functional Model is a simulation hardware component that connects to a PLBv46 bus and continously samples the bus signals.

The PLBv46 Master Bus Functional Model is a simulation hardware component that has a PLBv46 bus interface and may act as a bus master.

The CoreConnect Toolkit PLB Slave Bus Functional Model is a simulation hardware component that has a PLB bus interface and may act as a bus slave.

The CoreConnect Toolkit PLB Monitor Bus Functional Model is a simulation hardware component that connects to a PLB bus and continously samples the bus signals.

The CoreConnect Toolkit PLB Master Bus Functional Model is a simulation hardware component that has a PLB bus interface and may act as a bus master.

The CoreConnect Toolkit OPB Monitor Bus Functional Model is a simulation hardware component that connects to the OPB and continuously samples the bus signals.

The CoreConnect Toolkit OPB Device Bus Functional Model is a simulation hardware component that has an OPB bus interface and may act as a master, as a slave, or as both.

The BFM Synchronization Bus is a simple bus that connects the various Bus Functional Models in a design and allows communication between them.

The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-6 GTX transceivers is a customizable core that can be used to evaluate and monitor the health of Virtex-6 GTX Transceivers.

The ChipScope™ Pro IBERT core for Virtex®-6 GTX transceivers can be used to evaluate and monitor GTX transceivers. The design includes pattern generators and checkers implemented in FPGA logic, and access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers.

The ChipScope™ Pro IBERT core for Virtex®-5 FPGA GTX transceivers is a customizable core that can be used to evaluate and monitor Virtex-5 FPGA GTX transceivers.

The Xilinx® ChipScope™ Pro IBERT core for Spartan®-6 GTP transceivers is customizable and can be used to evaluate and monitor Spartan-6 GTP transceivers.

The Agilent Trace Core 2 (ATC2) is a customizable debug capture core that is specially designed to work with the latest generation logic analyzers from Agilent Technologies. The ATC2 core provides external Agilent logic analyzers access to internal FPGA design nets.

The Agilent Trace Core 2 (ATC2) is a customizable debug capture core that is specially designed to work with the latest generation logic analyzers from Agilent Technologies. The ATC2 core provides external Agilent logic analyzers access to internal FPGA design nets.

The Xilinx ChipScope™ Pro IBERT core for Virtex®-6 FPGA GTH transceivers is customizable and can be used to evaluate and monitor the GTH transceivers. The design includes pattern generators and checkers implemented in FPGA logic, and access to the ports and DRP attributes of the serial transceivers.

The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-5 GTP is a customizable core that can be used to evaluate and monitor the health of Virtex-5 GTP Transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the MGTs.

The ChipScope™ AXI Monitor core was designed to monitor and debug AXI interfaces. The core allows probing any signals going from a peripheral to the AXI interconnect. For instance, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor. This document contains information about the AXI4 version of the core.

The ChipScope™ AXI Monitor core was designed to monitor and debug AXI interfaces. The core allows probing any signals going from a peripheral to the AXI interconnect. For instance, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor. This document contains information about the AXI4 version of the core.

The ChipScope™ AXI Monitor core monitors and debugs AXI interfaces. The core allows probing any signals going from a peripheral to the AXI interconnect. For instance, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor. This document contains information about the AXI4 version of the core.

The ChipScope™ AXI Monitor core was designed to monitor and debug AXI interfaces. The core allows probing any signals going from a peripheral to the AXI interconnect. For instance, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor. This document contains information about the AXI4 version of the core.

The ChipScope™ AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the AXI interconnect. This document contains information about the AXI4 version of the core.

The ChipScope™ AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the AXI interconnect. This document contains information about the AXI4 version of the core.

The ChipScope™ Pro Integrated Bit Error Radio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that can be used to evaluate and monitor the health of Kintex-7 FPGA GTX transceivers.

The ChipScope™ Pro IBERT core for Kintex™-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Kintex-7 FPGA GTX transceivers.