Memory Interface

The AXI EMC (Advanced Microcontroller Bus Architecture (AMBA®) Advanced extensible Interface (AXI) External memory controller) provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to interface with the AXI 4 Interface.

The AXI System ACE™ Interface Controller (or, interchangeably, the AXI SYSACE) is the interface between AMBA® AXI4-Lite and the Microprocessor Unit (MPU) interface of the System ACE Compact Flash solution peripheral. This document contains information about the AXI4 version of the core.

The Xilinx LogiCORE™ Multichannel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynchronous SRAM and Flash memory devices through the MCH or PLB interfaces. It is assumed that the reader is familiar with the PLB and MCH protocol.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI Stream-type target peripherals. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory.

The AXI (Advanced eXtensible Interface) Direct Memory Access (AXI DMA) core is a soft Xilinx® Intellectual Property (IP) core providing high-bandwidth direct memory access between memory and AXI4-Stream-type target peripherals. Its optional scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor based systems.

The AXI-Stream FIFO core allows memory mapped access to a AXI-Stream interface. The core can be used to interface to the AXI Ethernet without the complexity or resource utilization of using DMA. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI VDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI VDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx® Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI Stream-type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI Stream-type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI VDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. This document contains information about the AXI4 version of the core.

The AXI External Memory Controller (EMC) IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to support the AXI4 interface.

The LogiCORE™ IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx® Embedded Development Kit (EDK). The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to local block RAM. The core supports both single and burst transactions to the block RAM and is optimized for performance. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory.

The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also off load data movement tasks from the Central Processing Unit (CPU) in processor based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

This is a data sheet for PLB Block RAM (BRAM) Interface Controller.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The AXI External Memory Controller (EMC) IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to support the AXI4 interface.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx® Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

This is the data sheet for the MCH_OPB Synchronous DRAM (SDRAM) Controller (v1.00a) core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

This is the data sheet for the OPB Synchronous DRAM (SDRAM) Controller (v1.00e) core

This application note details bridging an XSVI interface to an AXI4-Stream interface, enabling video designs with Xilinx video IP cores and XSVI interfaces to use the AXI VDMA.

Design File(s):

• xapp521.zip

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

The Advanced eXtensible Interface (AXI) Direct Memory Access (AXI DMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Xilinx® Embedded Development Kit (EDK) and the CORE Generator™ tools. The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI4-Stream-type target peripherals. This document contains information about the AXI4 version of the core.

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

The AXI EMC (Advanced Microcontroller Bus Architecture (AMBA®) Advanced extensible Interface (AXI) External memory controller) provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to interface with the AXI 4 Interface. This document contains information about the AXI4 version of the core.

The LogiCORE® IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Embedded Development Kit (EDK). The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to local block RAM. The core supports both single and burst transactions to the block RAM and is optimized for performance. This document contains information about the AXI4 version of the core.

The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

The XPS BRAM Interface Controller is a Xilinx IP module that incorporates a PLB V4.6 (Processor Local Bus) interface.

The AXI-Stream FIFO core allows memory mapped access to a AXI-Stream interface. The core can be used to interface to the AXI Ethernet without the complexity or resource utilization of using DMA. This document contains information about the AXI4 version of the core.

The AXI BRAM Controller is a soft LogiCORE™ Xilinx IP core that may be used with the Xilinx Embedded Development Kit (EDK) or made available as a stand alone core in the CORE Generator™ tool. The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to a local BRAM. This document contains information about the AXI4 version of the core.

The XPS Central DMA Controller provides simple Direct Memory Access (DMA) services to peripherals and memory devices on the PLB. The controller transfers a programmable quantity of data from a source address to a destination address without processor intervention.

The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory.

The XPS System ACE Interface Controller (or, interchangeably, the XPS SYSACE) is the interface between the Processor Local Bus (PLB) and the Microprocessor Interface (MPU) of the System ACE™ Compact Flash solution peripheral. This module attaches to the PLB.

The MMCM primitive in Virtex™-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. The MMCM module is a wrapper around the MMCM_ADV primitive that allows the MMCM to be used in the EDK tool suite.

The DMA SG service is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE™ products. It provides direct memory access (DMA) allowing for a bounded number of sequential data transfers to take place between regions in the address space, typically between memory and an I/O device, without processor management of individual transfers. This service also provides Scatter Gather (SG) functionality allowing a sequence of DMA operations to be prespecified by software and performed automatically without further processor intervention.

This is the data sheet for the Data-Side OCM BRAM (DSBRAM) Interface Controller (v3.00c) core.

This is the data sheet for the Channelized Direct Memory Access and Scatter Gather core.

This is the data sheet for the LMB BRAM Interface Controller (v2.10b) core.

This is the data sheet for the Instruction Side OCM Bus v1.0 (v2.00b) core

To communicate that Xilinx is discontinuing certain Development Systems products relates to LogiCORE™ IP, Image Processing Pipeline and Xilinx® Development Systems Kits and Boards Products on While Supplies Last.

This is the data sheet for the Instruction-Side OCM BRAM (ISBRAM) Interface Controller (v3.00c) core.

This is the data sheet for the Data Side OCM Bus v1.0 core

This is the data sheet for the Channel FIFO core

This application note provides the basic knowledge on how to integrate an embedded processor system with the Xilinx® Multi-Port Memory Controller (MPMC) and Video Frame Buffer Controller (VFBC) IP cores in System Generator for DSP (“System Generator”).

Design File(s):

• Design Files for xapp1136

This document provides the design specification for the Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller. This document contains information about the AXI4 version of the core.

The LogiCORE™ System Cache provides system level caching capability to an AMBA® AXI4 system. The System Cache resides in front of the external memory controller and is seen as a Level 2 Cache from the MicroBlaze™ processor point of view. This document contains information about the AXI4 version of the core.

The LogiCORE™ I/O Module is a highly integrated and light-weight implementation of a standard set of peripherals. The I/O Module is a standalone version of the tightly coupled I/O Module included in the LogiCORE MicroBlaze™ Micro Controller System (MCS). Using the I/O Module, a system equivalent to MicroBlaze MCS can be design using the ISE® Design Suite Embedded Edition.

This application note covers the design considerations of a video system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp741.zip

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface Central Direct Memory Access (AXI CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Xilinx® Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The LMB V10 module is used as the LMB interconnect for Xilinx® FPGA-based embedded processor systems. The LMB is a fast, local bus for connecting the MicroBlaze™ processor instruction and data ports to high-speed peripherals, primarily on-chip block RAM (BRAM).

This is the data sheet for the Local Memory Bus (LMB) V10 (v1.00a) core.

The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

This is the data sheet for the Channelized Direct Memory Access and Scatter Gather core.

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

This application note covers the design considerations of a video system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp741.zip

The DSOCM Bus core is a data-side On-Chip Memory (OCM) bus interconnect core. The core connects the PowerPC™ 405 data-side OCM interface to OCM peripherals, such as the data-side OCM BRAM controller (DSBRAM_IF_CNTRL).

This is the data sheet for the Data Side OCM Bus v1.0 core

This is the data sheet for the Data-Side OCM BRAM (DSBRAM) Interface Controller (v3.00c) core.

This is the data sheet for the Instruction Side OCM Bus v1.0 (v2.00b) core

This is the data sheet for the Instruction-Side OCM BRAM (ISBRAM) Interface Controller (v3.00c) core.

This is the data sheet for the Local Memory Bus (LMB) v1.0 (v1.00a) core.

The LMB V10 module is used as the LMB interconnect for Xilinx® FPGA-based embedded processor systems. The LMB is a fast, local bus for connecting the MicroBlaze™ processor instruction and data ports to high-speed peripherals, primarily on-chip block RAM (BRAM).

This is the data sheet for the Local Memory Bus (LMB) V10 (v1.00a) core.

This is the data sheet for the Multi-CHannel OPB External Memory Controller (MCH OPB EMC) (v1.00a) core.

This is the data sheet for the MCH_OPB Synchronous DRAM (SDRAM) Controller (v1.00a) core.

This is the data sheet for the OPB Block RAM (BRAM) Interface Controller core

This is the data sheet for the OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller (v2.00b) core.

This is the data sheet for the OPB External Memory Controller (OPB EMC) (2.00a) core

This is the data sheet for the OPB Synchronous DRAM (SDRAM) Controller (v1.00e) core

This is the data sheet for the PLB Synchronous DRAM (SDRAM) Controller.

This is the data sheet for the PLB Double Data Rate (DDR2) Synchronous DRAM (SDRAM) Controller (v1.01a) core

This data sheet is for the PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller.

This is a data sheet for PLB Block RAM (BRAM) Interface Controller.

The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory.

This application note provides the basic knowledge on how to integrate an embedded processor system with the Xilinx® Multi-Port Memory Controller (MPMC) and Video Frame Buffer Controller (VFBC) IP cores in System Generator for DSP (“System Generator”).

Design File(s):

• Design Files for xapp1136

The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory.

The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory.

The XPS Central DMA Controller provides simple Direct Memory Access (DMA) services to peripherals and memory devices on the PLB. The controller transfers a programmable quantity of data from a source address to a destination address without processor intervention.

This is the data sheet for the Multi-CHannel OPB Double Data Rate (DDR2) Synchronous DRAM (SDRAM) Controller core.

This is the data sheet for the MCH OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller core.

This is the data sheet for the OPB SYSACE (System ACE) Interface Controller (v1.00c) core

This is the data sheet for the PLB External Memory Controller (PLB EMC) (2.00a) core

This is the data sheet for the LMB BRAM Interface Controller (v2.10b) core.

This document provides the design specification for the Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller. This document contains information about the AXI4 version of the core.

This is the data sheet for the OPB Central DMA Controller core

The XPS BRAM Interface Controller is a Xilinx IP module that incorporates a PLB V4.6 (Processor Local Bus) interface.

The XPS System ACE Interface Controller (or, interchangeably, the XPS SYSACE) is the interface between the Processor Local Bus (PLB) and the Microprocessor Interface (MPU) of the System ACE™ Compact Flash solution peripheral. This module attaches to the PLB.

The Xilinx LogiCORE™ Multichannel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynchronous SRAM and Flash memory devices through the MCH or PLB interfaces. It is assumed that the reader is familiar with the PLB and MCH protocol.

The DMA SG service is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE™ products. It provides direct memory access (DMA) allowing for a bounded number of sequential data transfers to take place between regions in the address space, typically between memory and an I/O device, without processor management of individual transfers. This service also provides Scatter Gather (SG) functionality allowing a sequence of DMA operations to be prespecified by software and performed automatically without further processor intervention.

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

This is the data sheet for the Channel FIFO core

The MMCM primitive in Virtex™-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. The MMCM module is a wrapper around the MMCM_ADV primitive that allows the MMCM to be used in the EDK tool suite.

This data sheet describes the DDR2 Memory Controller reference design for the PowerPC® 440 block embedded in the Virtex®-5 FXT Platform FPGAs. The processor block interfaces with the Memory Controller Interface (MCI) and provides the control interface for DDR2 memory.

The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI Stream-type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI Stream-type target peripherals. This document contains information about the AXI4 version of the core.

The AXI (Advanced eXtensible Interface) Direct Memory Access (AXI DMA) core is a soft Xilinx® Intellectual Property (IP) core providing high-bandwidth direct memory access between memory and AXI4-Stream-type target peripherals. Its optional scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor based systems.

The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx® Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI Stream-type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also off load data movement tasks from the Central Processing Unit (CPU) in processor based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface (AXI) Direct Memory Access (AXI DMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Xilinx® Embedded Development Kit (EDK) and the CORE Generator™ tools. The AXI DMA engine provides high-bandwidth direct memory access between memory and AXI4-Stream-type target peripherals. This document contains information about the AXI4 version of the core.

The AXI EMC (Advanced Microcontroller Bus Architecture (AMBA®) Advanced extensible Interface (AXI) External memory controller) provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to interface with the AXI 4 Interface. This document contains information about the AXI4 version of the core.

The AXI EMC (Advanced Microcontroller Bus Architecture (AMBA®) Advanced extensible Interface (AXI) External memory controller) provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to interface with the AXI 4 Interface.

The AXI External Memory Controller (EMC) IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to support the AXI4 interface.

The AXI External Memory Controller (EMC) IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to support the AXI4 interface.

The AXI BRAM Controller is a soft LogiCORE™ Xilinx IP core that may be used with the Xilinx Embedded Development Kit (EDK) or made available as a stand alone core in the CORE Generator™ tool. The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to a local BRAM. This document contains information about the AXI4 version of the core.

The LogiCORE® IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Embedded Development Kit (EDK). The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to local block RAM. The core supports both single and burst transactions to the block RAM and is optimized for performance. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx® Embedded Development Kit (EDK). The core is designed as an AXI endpoint slave IP for integration with the AXI interconnect and system master devices to communicate to local block RAM. The core supports both single and burst transactions to the block RAM and is optimized for performance. This document contains information about the AXI4 version of the core.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx® Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory mapped source address and a memory mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface Central Direct Memory Access (AXI CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Xilinx® Embedded Development Kit (EDK). The AXI CDMA provides high-bandwidth direct memory access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI VDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI VDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI VDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

This application note details bridging an XSVI interface to an AXI4-Stream interface, enabling video designs with Xilinx video IP cores and XSVI interfaces to use the AXI VDMA.

Design File(s):

• xapp521.zip

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

This application note covers the design considerations of a video system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp741.zip

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx® IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.

The AXI-Stream FIFO core allows memory mapped access to a AXI-Stream interface. The core can be used to interface to the AXI Ethernet without the complexity or resource utilization of using DMA. This document contains information about the AXI4 version of the core.

The AXI-Stream FIFO core allows memory mapped access to a AXI-Stream interface. The core can be used to interface to the AXI Ethernet without the complexity or resource utilization of using DMA. This document contains information about the AXI4 version of the core.

The AXI System ACE™ Interface Controller (or, interchangeably, the AXI SYSACE) is the interface between AMBA® AXI4-Lite and the Microprocessor Unit (MPU) interface of the System ACE Compact Flash solution peripheral. This document contains information about the AXI4 version of the core.

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

The LogiCORE™ I/O Module is a highly integrated and light-weight implementation of a standard set of peripherals. The I/O Module is a standalone version of the tightly coupled I/O Module included in the LogiCORE MicroBlaze™ Micro Controller System (MCS). Using the I/O Module, a system equivalent to MicroBlaze MCS can be design using the ISE® Design Suite Embedded Edition.

The LogiCORE™ System Cache provides system level caching capability to an AMBA® AXI4 system. The System Cache resides in front of the external memory controller and is seen as a Level 2 Cache from the MicroBlaze™ processor point of view. This document contains information about the AXI4 version of the core.