Multi-Port Memory Controller (MPMC)

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Date	Name

03/01/2011	LogiCORE IP Multi-Port Memory Controller (MPMC) (v6.03.a) Data Sheet(PDF, ver 1.0, 2.7 MB ) The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory. Was this document helpful? Yes \| No
06/01/2009	XAPP1136 - Integrating a Video Frame Buffer Controller (VFBC) in System Generator Application Note(PDF, ver 1.0, 1.78 MB ) This application note provides the basic knowledge on how to integrate an embedded processor system with the Xilinx® Multi-Port Memory Controller (MPMC) and Video Frame Buffer Controller (VFBC) IP cores in System Generator for DSP (“System Generator”). Design File(s): Design Files for xapp1136 Was this document helpful? Yes \| No
07/06/2011	LogiCORE IP Multi-Port Memory Controller (MPMC) (v6.04.a) Data Sheet(PDF, ver 6.04.a, 2.62 MB ) The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory. Was this document helpful? Yes \| No
10/19/2011	LogiCORE IP Multi-Port Memory Controller (v6.05.a) Data Sheet(PDF, ver 3.0, 5.55 MB ) The LogiCORE™ IP Multi-Port Memory Controller is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR memory. Was this document helpful? Yes \| No