Peripheral (Networking)

This document provides the design specification for the HARD_TEMAC (Tri-mode Ethernet Media Access Controller) soft core. Tri-mode indicates that this core may transmit and receive data at three rates, 10, 100, or 1000 Megabits per second (Mb/s).

This is the data sheet for the XPS Ethernet Lite Media Access Controller (v4.00a) core.

This document provides the design specification for the AXI Ethernet core. This core can implement a tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC. It supports most popular PHY interfaces including 1000BASE-X and SGMII. This document contains information about the AXI4 version of the core.

This document provides the design specification for the XPS_LL_TEMAC soft Ethernet core.

This document provides the design specification for the AXI Ethernet core. This core can implement a tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC. It supports most popular PHY interfaces including 1000BASE-X and SGMII. This document contains information about the AXI4 version of the core.

This document provides the design specification for the AXI Ethernet core. This core can implement a tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC. It supports most popular PHY interfaces, including 1000BASE-X and SGMII. The core optionally supports Ethernet AVB (Audio Video Bridging) funct ions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers).

This application note describes how to use the lwIP library to add networking capability to an embedded system. In particular, lwIP is utilized to develop these applications: echo server, Web server, TFTP server and receive and transmit throughput tests.

Design File(s):

• Design files for XAPP1026

The LogiCORE™ IP AMBA® (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AMBA® AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. This document contains information about the AXI4 version of the core.

This document provides the design specification for the LogiCORE™ IP AXI Ethernet core. This core implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. It supports the most popular PHY interfaces, including 1000BASE-X and SGMII. The core optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.

The LogiCORE™ IP Utility Differential Signaling Buffer core generates corresponding buffer to bring off-chip differential signals into internal circuit or out from internal circuits. The core is intended as interconnect logic between off-chip differential signals and internal circuit.

This document provides the design specification for the LogiCORE™ IP AXI Ethernet core. This core implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. It supports the most popular PHY interfaces, including 1000BASE-X and SGMII. The core optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.

The LogiCORE™ IP AMBA® AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. This document contains information about the AXI4 version of the core.

This is the data sheet for the PLB TEMAC (v2.00a) core

Product specification for PLB 1-Gigabit Ethernet Media Access Controller (MAC) with DMA - PRELIMINARY.

This reference system provides a mechanism to access the Ethernet PHY registers.

Design File(s):

• MicroBlaze files for XAPP1042
• PPC files for XAPP1042

This is the data sheet for the XPS Ethernet Lite Media Access Controller (v4.00a) core.

This application note describes how to use the lwIP library to add networking capability to an embedded system. In particular, lwIP is utilized to develop these applications: echo server, Web server, TFTP server and receive and transmit throughput tests.

Design File(s):

• Design files for XAPP1026

This document provides the design specification for the XPS_LL_TEMAC soft Ethernet core.

This application note describes how to use the lwIP library to add networking capability to an embedded system. In particular, lwIP is utilized to develop these applications: echo server, Web server, TFTP server and receive and transmit throughput tests.

Design File(s):

• Design files for XAPP1026

This is the data sheet for the OPB Ethernet Lite Media Access Controller (v1.01b) core

This is the data sheet for the PLB Ethernet Media Access Controller (PLB_EMAC) - (v1.01a) core.

This document provides the design specification for the HARD_TEMAC (Tri-mode Ethernet Media Access Controller) soft core. Tri-mode indicates that this core may transmit and receive data at three rates, 10, 100, or 1000 Megabits per second (Mb/s).

The LogiCORE™ IP Utility Differential Signaling Buffer core generates corresponding buffer to bring off-chip differential signals into internal circuit or out from internal circuits. The core is intended as interconnect logic between off-chip differential signals and internal circuit.

This document provides the design specification for the AXI Ethernet core. This core can implement a tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC. It supports most popular PHY interfaces including 1000BASE-X and SGMII. This document contains information about the AXI4 version of the core.

This document provides the design specification for the AXI Ethernet core. This core can implement a tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC. It supports most popular PHY interfaces, including 1000BASE-X and SGMII. The core optionally supports Ethernet AVB (Audio Video Bridging) funct ions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers).

This document provides the design specification for the AXI Ethernet core. This core can implement a tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC. It supports most popular PHY interfaces including 1000BASE-X and SGMII. This document contains information about the AXI4 version of the core.

This document provides the design specification for the LogiCORE™ IP AXI Ethernet core. This core implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. It supports the most popular PHY interfaces, including 1000BASE-X and SGMII. The core optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.

This document provides the design specification for the LogiCORE™ IP AXI Ethernet core. This core implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. It supports the most popular PHY interfaces, including 1000BASE-X and SGMII. The core optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.optionally supports Ethernet AVB (Audio Video Bridging) functions. This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.

The LogiCORE™ IP AMBA® (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AMBA® AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AMBA® AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. This document contains information about the AXI4 version of the core.