Peripheral (UART, SPI, IIC, GPIO, Other)

The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to interface with the PLBV46.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the LogiCORE™ IP AXI IIC Bus Interface module. This document contains information about the AXI4 version of the core.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Advance Micro controller Bus Architecture Advanced eXtensible Interface (AXI) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN controller core. This document also defines the addressing and functionality of the various registers in the design, in addition to describing the user interface. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Lite (AXI) Timebase Watchdog Timer is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer. This document contains information about the AXI4 version of the core.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.

This product specification describes the functionality of the LogiCORE™ IP AXI HWICAP (Hardware ICAP) core for the AXI Interface. This core enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP). This enables a user to write software programs that modify the circuit structure and functionality during the operation of the circuit. This document contains information about the AXI4 version of the core.

This document describes the specifications for a Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) Timer/Counter core. This document contains information about the AXI4 version of the core.

The XPS Serial Peripheral Interface (SPI) connects to the PLB V4.6 (Processor Local Bus with Xilinx simplifications) and provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices.

The AXI GPIO provides a general purpose input/output interface to the AXI (Advanced eXtensible Interface) interface. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

This specification defines the architecture and interface requirements for the External Peripheral Controller (AXI EPC IP Core). The controller supports data transfers between the AXI4 (Advanced eXtensible Interface) and the external synchronous and/or asynchronous peripheral devices such as USB and LAN devices, which have processor interface. This document contains information about the AXI4 version of the core.

The AXI GPIO provides a general purpose input/output interface to the AXI (Advanced eXtensible Interface) interface. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The XPS SYSMON ADC IP core is a 32-bit slave peripheral that connects to the PLB (Processor Local Bus) and provides the controller interface for the System Monitor (SYSMON) hard macro on the Virtex®-5 and Virtex-6 family of FPGAs. This document describes the specifications for the XPS SYSMON ADC IP core.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLBv4.6) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the LogiCORE™ IP AXI IIC Bus Interface module. This document contains information about the AXI4 version of the core.

The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices. This document contains information about the AXI4 version of the core.

This product specification describes the functionality of the LogiCORE™ IP AXI HWICAP (Hardware ICAP) core for the AXI Interface. This core enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP). This enables a user to write software programs that modify the circuit structure and functionality during the operation of the circuit. This document contains information about the AXI4 version of the core.

This is the data sheet for the XPS 16550 UART (v3.00a) core

The XPS SYSMON ADC IP core is a 32-bit slave peripheral that connects to the PLB (Processor Local Bus) and provides the controller interface for the System Monitor (SYSMON) hard macro on the Virtex®-5 and Virtex-6 family of FPGAs. This document describes the specifications for the XPS SYSMON ADC IP core.

When digital systems are used in real-world applications, it is often necessary to convert an analog voltage level to a binary number. The value of this number is directly or inversely proportional to the voltage. The analog to digital conversion is realized in the XPS Delta-Sigma ADC (XPS ADC) using Delta-Sigma conversion technique. This soft IP core isdesigned to interface with the PLB (Processor Local Bus).

The InSystem Flash (ISF) is a type of serial flash memory and it is present only on Spartan®-3AN devices. The Spartan-3AN FPGA family is the sub-family of Spartan-3A FPGA devices.

This is the data sheet for the XPS External Peripheral Controller (EPC) v1.02a core.

This document describes the specifications for a Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) Timer/Counter core. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN controller core. This document also defines the addressing and functionality of the various registers in the design, in addition to describing the user interface. This document contains information about the AXI4 version of the core.

The XPS Interrupt Controller (XPS INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers for checking, enabling and acknowledging interrupts are accessed through a slave interface for the Processor Local Bus (PLB V4.6). The number of interrupts and other aspects can be tailored to the target system.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLBv4.6) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations.

The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to interface with the PLBV46.

This document describes the specifications for the General Purpose Input/Output (GPIO) core for the Processor Local Bus (PLB). The XPS GPIO is a 32-bit peripheral that attaches to the PLBv4.6.

The AXI GPIO provides a general purpose input/output interface to the AXI (Advanced eXtensible Interface) interface. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Advance Micro controller Bus Architecture Advanced eXtensible Interface (AXI) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN controller core. This document also defines the addressing and functionality of the various registers in the design, in addition to describing the user interface.

This document describes the specifications for a XPS Timer/Counter core for the Processor Local Bus.

This is the data sheet for the Fixed Interval Timer (FIT) (v1.01b) core.

The digital to analog converter (DAC) converts a binary number into a voltage directly proportional to the value of the binary number. A variety of applications use DAC including waveform generators and programmable voltage sources.

The MGT Protector core puts uninstantiated Multi-Gigabit Transceivers (MGTs) on the device into a safe activity mode.

The LogiCORE™ IP AXI Sysmon ADC core is a 32-bit slave peripheral that connects to the AXI (Advanced eXtensible Interface) and provides the controller interface for the System Monitor (SYSMON) hard macro on Virtex®-6 family of FPGAs. This document describes the specifications for the AXI Sysmon ADC core. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) and provides the controller interface for asynchronous serial data transfer. This soft LogiCORE IP core is designed to interface with the AXI4-Lite protocol. This document contains information about the AXI4 version of the core.

The LogiCORE™ Media Oriented Systems Transport (MOST®) Network Interface Controller (NIC) core is a controller designed to the MOST Specification revision 2.4. When combined with the Xilinx Automotive solution and embedded processing, the MOST NIC core allows the user to take advantage of the MOST open standard network by providing a higher level of customization in a scalable, flexible design solution.

The XPS Timebase Watchdog Timer Interface is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer.

This is the data sheet for the DCR Interrupt Controller (v2.00a) core.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLBv4.6) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations.

The LogiCORE™ IP XPS PS2 Controller is a PLB (Processor Local Bus) slave that is designed to control PS2 devices such as keyboard and mouse. The PS2 protocol is a simple bidirectional serial protocol.

The Xilinx® Universal Serial Bus 2.0 High Speed Device with an AMBA® AXI interface enables USB connectivity to a design using a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges and legacy port replacement operations. This document contains information about the AXI4 version of the core.

This is the data sheet for the OPB 16450 UART core

This is the data sheet for the OPB Timer/Counter (v1.00b) core

This is the data sheet for the OPB Timebase WDT (v1.00a) core

This is the data sheet for the OPB Serial Peripheral Interface (SPI) (v1.00e) core.

This is the data sheet for the OPB IIC Bus Interface (v1.01d) core.

This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC). The controller supports data transfers between the On-Chip Peripheral Bus (OPB) and the external synchronous and/or asynchronous peripheral devices.

The Xilinx® Universal Serial Bus 2.0 High Speed Device with an AMBA® AXI interface enables USB connectivity to a design using a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges and legacy port replacement operations. This document contains information about the AXI4 version of the core.

This document describes the specifications for a Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) Timer/Counter core. The AXI Timer/Counter is a 32/64-bit timer module that attaches to the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices. This document contains information about the AXI4 version of the core.

The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA® (Advance Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to connect via an AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) and provides the controller interface for asynchronous serial data transfer. This soft LogiCORE IP core is designed to interface with the AXI4-Lite protocol.

The Xilinx® LogiCORE™ IP Advanced eXtensible Interface (AXI) HWICAP (Hardware Internal Configuration Access Port) core for the AXI Interface enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP/ICAPE2). This enables you to write software programs that modify the circuit structure and functionality during the operation of the circuit. This document contains information about the AXI4 version of the core.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the LogiCORE™ IP AXI IIC Bus Interface module. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Advanced eXtensible Interface (AXI) Xilinx® Analog-to-Digital Converter (XADC) core is a 32-bit slave peripheral that connects to the AXI4 interface and provides the controller interface for System Monitor XADC hard macro on Zynq™-7000 devices and 7 series FPGAs. This document contains information about the AXI4 version of the core.

This is the data sheet for the DCR Interrupt Controller (v2.00a) core.

This is the data sheet for the Fixed Interval Timer (FIT) (v1.01b) core.

This is the data sheet for the OPB 16550 UART (v1.00d) core.

This is the data sheet for the OPB Delta-Sigma Analog to Digital Converter (ADC) (v1.01a) core

This is the data sheet for the OPB Delta-Sigma DAC (v1.01a) core

This is the data sheet for the OPB Interrupt Controller (v1.00c) core.

This is the data sheet for the OPB IIC Bus Interface (v1.01d) core.

This is the data sheet for the OPB Serial Peripheral Interface (SPI) (v1.00e) core.

This is the data sheet for the OPB Timer/Counter (v1.00b) core

The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLBv4.6) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLBv4.6) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLBv4.6) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations.

The XPS Serial Peripheral Interface (SPI) connects to the PLB V4.6 (Processor Local Bus with Xilinx simplifications) and provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.

This application note describes a reference system to test the operation of Xilinx Platform Studio (XPS) Controller Area Network (CAN) cores that are connected to each other using CAN PHYs on the XA3S1600E board, which is part of the XA Automotive Development Kit.

Design File(s):

• XAPP1056 Reference System: CAN Using the XA Automotive ECU Development Kit

The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN controller core. This document also defines the addressing and functionality of the various registers in the design, in addition to describing the user interface.

This is the data sheet for the PLB 16550 UART (v1.00c).

This is the data sheet for the PLB 16450 UART (v1.00c).

This is the data sheet for the PLB General Purpose Input/Output (GPIO) (v1.00b) core

This is the data sheet for the OPB Timebase WDT (v1.00a) core

This is the data sheet for the OPB 16450 UART core

This is the data sheet for the XPS 16550 UART (v3.00a) core

This is the data sheet for the XPS FlexRay™ Controller (v1.00a) core

The LogiCORE™ Media Oriented Systems Transport (MOST®) Network Interface Controller (NIC) core is a controller designed to the MOST Specification revision 2.4. When combined with the Xilinx Automotive solution and embedded processing, the MOST NIC core allows the user to take advantage of the MOST open standard network by providing a higher level of customization in a scalable, flexible design solution.

The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to interface with the PLBV46.

The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to interface with the PLBV46.

This is the data sheet for the OPB HWICAP core.

This document describes the specifications for the General Purpose Input/Output (GPIO) core for the Processor Local Bus (PLB). The XPS GPIO is a 32-bit peripheral that attaches to the PLBv4.6.

When digital systems are used in real-world applications, it is often necessary to convert an analog voltage level to a binary number. The value of this number is directly or inversely proportional to the voltage. The analog to digital conversion is realized in the XPS Delta-Sigma ADC (XPS ADC) using Delta-Sigma conversion technique. This soft IP core isdesigned to interface with the PLB (Processor Local Bus).

The digital to analog converter (DAC) converts a binary number into a voltage directly proportional to the value of the binary number. A variety of applications use DAC including waveform generators and programmable voltage sources.

The XPS Interrupt Controller (XPS INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers for checking, enabling and acknowledging interrupts are accessed through a slave interface for the Processor Local Bus (PLB V4.6). The number of interrupts and other aspects can be tailored to the target system.

The XPS SYSMON ADC IP core is a 32-bit slave peripheral that connects to the PLB (Processor Local Bus) and provides the controller interface for the System Monitor (SYSMON) hard macro on the Virtex®-5 and Virtex-6 family of FPGAs. This document describes the specifications for the XPS SYSMON ADC IP core.

The XPS SYSMON ADC IP core is a 32-bit slave peripheral that connects to the PLB (Processor Local Bus) and provides the controller interface for the System Monitor (SYSMON) hard macro on the Virtex®-5 and Virtex-6 family of FPGAs. This document describes the specifications for the XPS SYSMON ADC IP core.

The XPS Timebase Watchdog Timer Interface is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer.

This document describes the specifications for a XPS Timer/Counter core for the Processor Local Bus.

This is the data sheet for the XPS External Peripheral Controller (EPC) v1.02a core.

The LogiCORE™ IP XPS PS2 Controller is a PLB (Processor Local Bus) slave that is designed to control PS2 devices such as keyboard and mouse. The PS2 protocol is a simple bidirectional serial protocol.

The InSystem Flash (ISF) is a type of serial flash memory and it is present only on Spartan®-3AN devices. The Spartan-3AN FPGA family is the sub-family of Spartan-3A FPGA devices.

This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC). The controller supports data transfers between the On-Chip Peripheral Bus (OPB) and the external synchronous and/or asynchronous peripheral devices.

The MGT Protector core puts uninstantiated Multi-Gigabit Transceivers (MGTs) on the device into a safe activity mode.

This document describes the specifications for a Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) Timer/Counter core. This document contains information about the AXI4 version of the core.

This document describes the specifications for a Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) Timer/Counter core. This document contains information about the AXI4 version of the core.

This document describes the specifications for a Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) Timer/Counter core. The AXI Timer/Counter is a 32/64-bit timer module that attaches to the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Lite (AXI) Timebase Watchdog Timer is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) and provides the controller interface for asynchronous serial data transfer. This soft LogiCORE IP core is designed to interface with the AXI4-Lite protocol. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture (AMBA®) specification’s Advanced eXtensible Interface (AXI) and provides the controller interface for asynchronous serial data transfer. This soft LogiCORE IP core is designed to interface with the AXI4-Lite protocol.

The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA® (Advance Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to connect via an AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The AXI GPIO provides a general purpose input/output interface to the AXI (Advanced eXtensible Interface) interface. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The AXI GPIO provides a general purpose input/output interface to the AXI (Advanced eXtensible Interface) interface. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The AXI GPIO provides a general purpose input/output interface to the AXI (Advanced eXtensible Interface) interface. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface. This document contains information about the AXI4 version of the core.

The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices. This document contains information about the AXI4 version of the core.

The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN controller core. This document also defines the addressing and functionality of the various registers in the design, in addition to describing the user interface. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN controller core. This document also defines the addressing and functionality of the various registers in the design, in addition to describing the user interface. This document contains information about the AXI4 version of the core.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the LogiCORE™ IP AXI IIC Bus Interface module. This document contains information about the AXI4 version of the core.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the LogiCORE™ IP AXI IIC Bus Interface module. This document contains information about the AXI4 version of the core.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the LogiCORE™ IP AXI IIC Bus Interface module. This document contains information about the AXI4 version of the core.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Advance Micro controller Bus Architecture Advanced eXtensible Interface (AXI) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations. This document contains information about the AXI4 version of the core.

The Xilinx Universal Serial Bus 2.0 High Speed Device with Advance Micro controller Bus Architecture Advanced eXtensible Interface (AXI) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations. This document contains information about the AXI4 version of the core.

The Xilinx® Universal Serial Bus 2.0 High Speed Device with an AMBA® AXI interface enables USB connectivity to a design using a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges and legacy port replacement operations. This document contains information about the AXI4 version of the core.

The Xilinx® Universal Serial Bus 2.0 High Speed Device with an AMBA® AXI interface enables USB connectivity to a design using a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges and legacy port replacement operations. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Sysmon ADC core is a 32-bit slave peripheral that connects to the AXI (Advanced eXtensible Interface) and provides the controller interface for the System Monitor (SYSMON) hard macro on Virtex®-6 family of FPGAs. This document describes the specifications for the AXI Sysmon ADC core. This document contains information about the AXI4 version of the core.

This product specification describes the functionality of the LogiCORE™ IP AXI HWICAP (Hardware ICAP) core for the AXI Interface. This core enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP). This enables a user to write software programs that modify the circuit structure and functionality during the operation of the circuit. This document contains information about the AXI4 version of the core.

This product specification describes the functionality of the LogiCORE™ IP AXI HWICAP (Hardware ICAP) core for the AXI Interface. This core enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP). This enables a user to write software programs that modify the circuit structure and functionality during the operation of the circuit. This document contains information about the AXI4 version of the core.

The Xilinx® LogiCORE™ IP Advanced eXtensible Interface (AXI) HWICAP (Hardware Internal Configuration Access Port) core for the AXI Interface enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP/ICAPE2). This enables you to write software programs that modify the circuit structure and functionality during the operation of the circuit. This document contains information about the AXI4 version of the core.

This specification defines the architecture and interface requirements for the External Peripheral Controller (AXI EPC IP Core). The controller supports data transfers between the AXI4 (Advanced eXtensible Interface) and the external synchronous and/or asynchronous peripheral devices such as USB and LAN devices, which have processor interface. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP Advanced eXtensible Interface (AXI) Xilinx® Analog-to-Digital Converter (XADC) core is a 32-bit slave peripheral that connects to the AXI4 interface and provides the controller interface for System Monitor XADC hard macro on Zynq™-7000 devices and 7 series FPGAs. This document contains information about the AXI4 version of the core.