Peripheral (PCI, PCIe)

The PLBV46 PCI™ Full Bridge design provides full bridge functionality between the Xilinx® PLB and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI™) bus.

This document defines the functional operation of the PLBv46 Root Complex and Endpoint Bridge for PCI Express®, hereafter called PLBv46 Bridge. The PLBv46 Bridge is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) bus.

This document defines the functional operation of the PLBv46 Root Complex and Endpoint Bridge for PCI Express®, hereafter called PLBv46 Bridge. The PLBv46 Bridge is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) bus.

This is the data sheet for the OPB PCI Full Bridge (v1.02a) core

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express® core. C code running on the PowerPC® 440 drives the EDK system.

Design File(s):

• Design file for XAPP1111

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express®.

Design File(s):

• Design file for XAPP1110

The PCI Arbiter provides arbitration for two to eight PCI master agents.

To communicate that Xilinx is discontinuing certain Development Systems products relates to LogiCORE™ IP, Image Processing Pipeline and Xilinx® Development Systems Kits and Boards Products on While Supplies Last.

The Advanced eXtensible Interface (AXI) Endpoint (EP) Bridge for PCI Express® is an interface between the AXI4 bus and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that need to be implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface (AXI) Root Complex/Endpoint (RC/EP) Bridge for PCI Express® is an interface between the AXI4 and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that are implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface (AXI) Root Port/Endpoint (RP/EP) Bridge for PCI Express® is an interface between the AXI4 and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that are implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.

The PCI Arbiter provides arbitration for two to eight PCI master agents.

This is the data sheet for the OPB PCI Arbiter core

This is the data sheet for the OPB PCI Full Bridge (v1.02a) core

The OPB PCI User Guide provides design information on using the OPB PCI Full Bridge core in Virtex™-II Pro, Virtex-4, and Spartan™ FPGAs.

Design File(s):

• ug241.zip

This application note describes how to build a reference system for the Processor Local Bus Peripheral Component Interconnect (PLBv46 PCI) Core using the MicroBlaze™ processor-based embedded system in the Avnet Spartan™-3 Evaluation Board.

Design File(s):

• Reference System: PLBv46 PCI Using the Avnet Spartan-3 FPGA Evaluation Board

This is the data sheet for the PLBV46 PCI Full Bridge (v1.00a) core

The PLBV46 PCI™ Full Bridge design provides full bridge functionality between the Xilinx® PLB and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI™) bus.

This is the data sheet for the PLB PCI Full Bridge (v1.00a) core

This document defines the functional operation of the PLBv46 Root Complex and Endpoint Bridge for PCI Express®, hereafter called PLBv46 Bridge. The PLBv46 Bridge is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) bus.

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML555 PCI/PCI Express Development Platform.

Design File(s):

• Design File for XAPP1000

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML505 Embedded Development Platform.

Design File(s):

• Design File for XAPP1030

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML507 Embedded Development Platform.

Design File(s):

• xapp1040.zip

This document defines the functional operation of the PLBv46 Root Complex and Endpoint Bridge for PCI Express®, hereafter called PLBv46 Bridge. The PLBv46 Bridge is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) bus.

The Advanced eXtensible Interface (AXI) Endpoint (EP) Bridge for PCI Express® is an interface between the AXI4 bus and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that need to be implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface (AXI) Endpoint (EP) Bridge for PCI Express® is an interface between the AXI4 bus and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that need to be implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface (AXI) Root Complex/Endpoint (RC/EP) Bridge for PCI Express® is an interface between the AXI4 and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that are implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.

The Advanced eXtensible Interface (AXI) Root Port/Endpoint (RP/EP) Bridge for PCI Express® is an interface between the AXI4 and PCI Express. Definitions and references are provided in this document for all of the functional modules, registers, and interfaces that are implemented in the AXI Bridge for PCI Express. This document contains information about the AXI4 version of the core.