Processor Core

The PicoBlaze™ embedded microcontroller is an efficient, cost-effective embedded processor core for Spartan®-3, Spartan-6, Virtex®-5, and Virtex-6 FPGAs. This user guide describes the capabilities, features, and benefits of PicoBlaze hardware design and how to effectively use the PicoBlaze instruction set and tools to create software applications.

Design File(s):

• ip_product_details.jsp?key=picoblaze-S3-V2-Pro

The PPC440 Virtex®-5 is a wrapper around the Virtex-5 Embedded Block primitive.

This is the data sheet for the OPB SYSACE (System ACE) Interface Controller (v1.00c) core

This data sheet describes the DDR2 Memory Controller reference design for the PowerPC® 440 block embedded in the Virtex®-5 FXT Platform FPGAs. The processor block interfaces with the Memory Controller Interface (MCI) and provides the control interface for DDR2 memory.

The PPC405 Virtex®-4 is a wrapper around the Virtex-4 PowerPC™ 405 Processor Block primitive.

This is the data sheet for the PLB Asynchronous Transfer Mode Controller (PLB_ATMC) (v1.00a) core

The AXI External Master Connector (axi_ext_master_conn), lets you connect an AXI master device outside of the embedded system module, using embedded module ports, to the slave interface of an AXI Interconnect IP with no intervening logic. This document contains information about the AXI4 version of the core.

The Utility Flip-Flop is a pipelining glue-logic core intended for use in a Xilinx Platform Studio (XPS) project.

This is the data sheet for the PLB Asynchronous Transfer Mode Controller (PLB_ATMC) core

This data sheet is for the APU Floating-Point Unit v3.1 core.

This document provides the design specification for the Xilinx MicroBlaze Trace Core (XMTC), which provides instruction and data trace capabilities for MicroBlaze™ processors.

The Utility Reduced Logic core applies a logic reduction function over an input vector to generate a single bit result. The core is intended as glue logic between peripherals.

The Utility Vector Logic core takes two vector operands and bit wise applies a logic function to generate a single vector result. This core is intended as glue logic between peripherals.

The Xilinx LogiCORE™ IP Auxiliary Processor Unit (APU) Floating-Point Unit is an optimized floating-point unit designed for the PowerPC™ 440 embedded microprocessor of the Virtex®-5 FXT FPGA family. The FPU implementation provides support for IEEE-754 floating-point arithmetic operations in single or double precision.

The Processing System 7 IP is the software interface around the Zynq Processing System. The Zynq™-7000 family consists of an system-on-chip (SoC) style integrated processing system (PS) and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.

AXI External Slave Connector (axi_ext_slave_conn), lets you connect an AXI slave device outside of the embedded system module, using embedded module ports, to the master interface of an AXI Interconnect IP without intervening logic. This document contains information about the AXI4 version of the core.

This data sheet is for the APU Floating-Point Unit v3.1 core.

The Xilinx LogiCORE™ IP Auxiliary Processor Unit (APU) Floating-Point Unit is an optimized floating-point unit designed for the PowerPC™ 440 embedded microprocessor of the Virtex®-5 FXT FPGA family. The FPU implementation provides support for IEEE-754 floating-point arithmetic operations in single or double precision.

This document provides the design specification for the Xilinx MicroBlaze Trace Core (XMTC), which provides instruction and data trace capabilities for MicroBlaze™ processors.

This contains reference systems for the Spartan®-3A DSP 3SD1800A MicroBlaze™ Reference Systems

Design File(s):

• MicroBlaze Processor Kit Reference Systems
• Design file for UG486

This white paper describes the fully-functional, tested, and supported targeted reference designs for both the Spartan®-6 and Virtex®-6 FPGAs.

This user guide showcases various features of the Virtex®-5 FXT FPGA ML507 development board. It describes the hardware platform, the HelloWorld software application, and the BlueCat Linux images.

Design File(s):

• ug511_mb_emb_ref.zip
• ug511_ppc440_emb_ref.zip

The MicroBlaze® Processor Reference Guide provides information about the 32-bit soft processor, MicroBlaze, which is part of the Embedded Processor Development Kit (EDK). The document is intended as a guide to the MicroBlaze hardware architecture.

This guide serves as a technical reference describing the hardware interface to the PowerPC® 405 processor block. It contains information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation.

This document provides an introduction as well as operational concepts, user programming model, PPC405 privileged-mode programming model, memory-system management, and virtual-memory management.

This is the data sheet for the PPC405 (Wrapper) core.

This tutorial provides the steps necessary to implement a Virtex™-4 FX PowerPC™ 405 system with floating point coprocessor using Xilinx Platform Studio software.

The PPC405 Virtex®-4 is a wrapper around the Virtex-4 PowerPC™ 405 Processor Block primitive.

This guide serves as a technical reference describing the hardware interface to the PowerPC® 405 processor block. It contains information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation.

This document provides an introduction as well as operational concepts, user programming model, PPC405 privileged-mode programming model, memory-system management, and virtual-memory management.

The PPC440 Virtex®-5 is a wrapper around the Virtex-5 Embedded Block primitive.

This data sheet describes the DDR2 Memory Controller reference design for the PowerPC® 440 block embedded in the Virtex®-5 FXT Platform FPGAs. The processor block interfaces with the Memory Controller Interface (MCI) and provides the control interface for DDR2 memory.

This application note illustrates how to simulate PowerPC® 440 systems.

Design File(s):

• Design file for XAPP1003

This user guide showcases various features of the Virtex®-5 FXT FPGA ML507 development board. It describes the hardware platform, the HelloWorld software application, and the BlueCat Linux images.

Design File(s):

• ug511_mb_emb_ref.zip
• ug511_ppc440_emb_ref.zip

This reference guide describes the embedded processor block available in the Virtex®-5 FXT device.

The PicoBlaze™ embedded microcontroller is an efficient, cost-effective embedded processor core for Spartan®-3, Spartan-6, Virtex®-5, and Virtex-6 FPGAs. This user guide describes the capabilities, features, and benefits of PicoBlaze hardware design and how to effectively use the PicoBlaze instruction set and tools to create software applications.

Design File(s):

• ip_product_details.jsp?key=picoblaze-S3-V2-Pro

The Utility Vector Logic core takes two vector operands and bit wise applies a logic function to generate a single vector result. This core is intended as glue logic between peripherals.

The Utility Reduced Logic core applies a logic reduction function over an input vector to generate a single bit result. The core is intended as glue logic between peripherals.

The Utility Flip-Flop is a pipelining glue-logic core intended for use in a Xilinx Platform Studio (XPS) project.

The AXI External Master Connector (axi_ext_master_conn), lets you connect an AXI master device outside of the embedded system module, using embedded module ports, to the slave interface of an AXI Interconnect IP with no intervening logic. This document contains information about the AXI4 version of the core.

AXI External Slave Connector (axi_ext_slave_conn), lets you connect an AXI slave device outside of the embedded system module, using embedded module ports, to the master interface of an AXI Interconnect IP without intervening logic. This document contains information about the AXI4 version of the core.

The Processing System 7 IP is the software interface around the Zynq Processing System. The Zynq™-7000 family consists of an system-on-chip (SoC) style integrated processing system (PS) and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.