Processor Interface

The AXI Master Lite is an AXI4-compatible LogiCORE™ IP product. It provides an interface between a user-created IP core and an AXI4-Lite interface. The AXI4-Lite Master IP supports AXI4-Lite compatible bus mastering operations which are single 32-bit wide read or write data transfers.

This product specification describes the functionality of the HWICAP core for the Processor Local Bus (PLB). The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC® to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP) at run time, which enables a user to write software programs for an embedded processor that modifies the circuit structure and functionality during the circuit’s operation.

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers used for checking, enabling, and acknowledging interrupts are accessed through a slave interface for the AMBA® protocol’s AXI (Advanced Micro controller Bus Architecture Advanced eXtensible Interface) specification. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Slave Burst is an interface between the AXI4 memory-mapped interface to the IPIC (IP Inter Connect). This core is designed to provide a smooth migration path to the burst-supported IP from PLBv46 to AXI4 with minor updates in the interface. The core provides a point to point bi-directional interface between a user IP core and the AXI4 interconnect. This core acts as master on IPIC while it behaves as a slave on AXI4. This document contains information about the AXI4 version of the core.

The AXI-to-AXI Connector (axi2axi_connector), lets a slave interface of one AXI Interconnect module connect to the master interface of another AXI Interconnect with no intervening logic. The axi2axi_connector IP provides the port connection points necessary to represent the connectivity in the system, plus a set of parameters used to configure the interfaces of the AXI Interconnect modules being connected. This document contains information about the AXI4 version of the core.

The Interrupt Control service is a continuation of the Xilinx® family of IBM CoreConnect-compatible LogiCORE™ products. It provides interrupt capture support for internal IPIF sub-block as well as support for the connected IP function.

In a multi-processor environment, the processors share common resources. The Mutex core provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. This document contains information about the AXI4 version of the core.

The XPS LL FIFO is a soft IP core designed for Xilinx FPGAs. This core allows memory mapped access to a LocalLink interface. The core can be used to interface to the XPS LL TEMAC without the need to use DMA. Other uses include interfacing to the LocalLink interfaces on PLBv46 PCIe and PLBv46 PCI.

In a multiprocessor environment, the processors need to communicate data with each other. The easiest method is to set up inter-processor communication through a mailbox. Mailbox features a bi-directional communication channel between two processors. This document contains information about the AXI4 version of the core.

The Clock Generator core takes in common clock requirement through its parameters and generates the architecture-specific clocking circuitry. The circuitry is implemented in a VHDL source.

This is the data sheet for the Fast Simplex Link (FSL) Bus (v2.11c) core.

The Phase Locked Loop primitive in Virtex®-5FXT parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock.

This product specification describes the functionality of the HWICAP core for the Processor Local Bus (PLB). The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC® to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP) at run time, which enables a user to write software programs for an embedded processor that modifies the circuit structure and functionality during the circuit’s operation.

This is the data sheet for the XPS Mailbox (v2.00a) core.

This is the data sheet for the JTAGPPC Controller (v2.01c) core.

This is the data sheet for the Digital Clock Manager (DCM) Module core

The Utility IO Multiplexer module provides a multiplexing function between two IO vectors to one IO vector.

The Xilinx Processor System Reset Module design allows customers to tailor their designs to suit their application by setting certain parameters to enable/disable features.

This is the data sheet for the XPS Mutex (v1.00.c) core.

The AXI Master Lite is an AXI4-compatible LogiCORE™ IP product. It provides an interface between a user-created IP core and an AXI4-Lite interface. The AXI4-Lite Master IP supports AXI4-Lite compatible bus mastering operations which are single 32-bit wide read or write data transfers.

The AMBA® (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) to APB (Advanced Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions. It functions as a slave on the AXI4-Lite interface and as a master on the APB interface. The AXI to APB Bridge main use model is to connect the APB slaves with AXI masters. This document contains information about the AXI4 version of the core.

The AXI Interconnect IP (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The Clock Generator core takes in common clock requirement through its parameters and generates the architecture-specific clocking circuitry. The circuitry is implemented in a VHDL source.

The AXI Master Burst is a continuation of the Xilinx family of AXI4-compatible LogiCORE™ IP products. It provides a bidirectional interface between a User IP core and the AXI4 interface standard. This version of the AXI Master Burst has been optimized for bus mastering operations consisting of burst transactions. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The PLB Central DMA Controller provides simple Direct Memory Access (DMA) services to peripherals and memory devices on the PLB. The controller transfers a programmable quantity of data from a source address to a destination address without processor intervention.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The AXI Lite IPIF is a part of the Xilinx family of Advanced RISC Machine (ARM®) Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point bi-directional interface between a user IP core and the AXI interconnect. This document contains information about the AXI4 version of the core.

The Clock Generator core takes in common clock requirement through its parameters and generates the architecture-specific clocking circuitry. The circuitry is implemented in a VHDL source.

The Xilinx® LogiCORE™ IP Processor System Reset Module core provides customized resets for an entire processor system, including the processor, the interconnect and peripherals. The core allows customers to tailor their designs to suit their application by setting certain parameters to enable/disable features.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers used for storing interrupt vector addresses, checking, enabling and acknowledging interrupts are accessed through a slave interface for the AMBA® AXI (Advanced eXtensible Interface) specification. The number of interrupts and other aspects can be tailored to the target system. This document contains information about the AXI4 version of the core.

The Clock Generator core takes in common clock requirement through its parameters and generates the architecture-specific clocking circuitry. The circuitry is implemented in a VHDL source.

The Clock Generator core takes in common clock requirement through its parameters and generates the architecture-specific clocking circuitry. The circuitry is implemented in a VHDL source.

The Clock Generator core takes in common clock requirement through its parameters and generates the architecture-specific clocking circuitry. The circuitry is implemented in a VHDL source.

This is the data sheet for the JTAGPPC Controller (v2.01c) core.

The Xilinx Processor System Reset Module design allows customers to tailor their designs to suit their application by setting certain parameters to enable/disable features.

The Xilinx® LogiCORE™ IP Processor System Reset Module core provides customized resets for an entire processor system, including the processor, the interconnect and peripherals. The core allows customers to tailor their designs to suit their application by setting certain parameters to enable/disable features.

This is the data sheet for the XPS Mailbox (v2.00a) core.

This is the data sheet for the XPS Mutex (v1.00.c) core.

This is the data sheet for the Fast Simplex Link (FSL) Bus (v2.11c) core.

This is the data sheet for the Digital Clock Manager (DCM) Module core

The PLB Central DMA Controller provides simple Direct Memory Access (DMA) services to peripherals and memory devices on the PLB. The controller transfers a programmable quantity of data from a source address to a destination address without processor intervention.

The XPS LL FIFO is a soft IP core designed for Xilinx FPGAs. This core allows memory mapped access to a LocalLink interface. The core can be used to interface to the XPS LL TEMAC without the need to use DMA. Other uses include interfacing to the LocalLink interfaces on PLBv46 PCIe and PLBv46 PCI.

This product specification describes the functionality of the HWICAP core for the Processor Local Bus (PLB). The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC® to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP) at run time, which enables a user to write software programs for an embedded processor that modifies the circuit structure and functionality during the circuit’s operation.

This product specification describes the functionality of the HWICAP core for the Processor Local Bus (PLB). The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC® to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP) at run time, which enables a user to write software programs for an embedded processor that modifies the circuit structure and functionality during the circuit’s operation.

The Phase Locked Loop primitive in Virtex®-5FXT parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock.

The Interrupt Control service is a continuation of the Xilinx® family of IBM CoreConnect-compatible LogiCORE™ products. It provides interrupt capture support for internal IPIF sub-block as well as support for the connected IP function.

The Utility IO Multiplexer module provides a multiplexing function between two IO vectors to one IO vector.

The AXI Interconnect IP (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interconnect (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specification from ARM®, including the AXI4-Lite control register interface subset. This document contains information about the AXI4 version of the core.

The AXI Lite IPIF is a part of the Xilinx family of Advanced RISC Machine (ARM®) Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point bi-directional interface between a user IP core and the AXI interconnect. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Slave Burst is an interface between the AXI4 memory-mapped interface to the IPIC (IP Inter Connect). This core is designed to provide a smooth migration path to the burst-supported IP from PLBv46 to AXI4 with minor updates in the interface. The core provides a point to point bi-directional interface between a user IP core and the AXI4 interconnect. This core acts as master on IPIC while it behaves as a slave on AXI4. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers used for checking, enabling, and acknowledging interrupts are accessed through a slave interface for the AMBA® protocol’s AXI (Advanced Micro controller Bus Architecture Advanced eXtensible Interface) specification. This document contains information about the AXI4 version of the core.

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers used for storing interrupt vector addresses, checking, enabling and acknowledging interrupts are accessed through a slave interface for the AMBA® AXI (Advanced eXtensible Interface) specification. The number of interrupts and other aspects can be tailored to the target system. This document contains information about the AXI4 version of the core.

The AMBA® (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) to APB (Advanced Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions. It functions as a slave on the AXI4-Lite interface and as a master on the APB interface. The AXI to APB Bridge main use model is to connect the APB slaves with AXI masters. This document contains information about the AXI4 version of the core.

The AXI-to-AXI Connector (axi2axi_connector), lets a slave interface of one AXI Interconnect module connect to the master interface of another AXI Interconnect with no intervening logic. The axi2axi_connector IP provides the port connection points necessary to represent the connectivity in the system, plus a set of parameters used to configure the interfaces of the AXI Interconnect modules being connected. This document contains information about the AXI4 version of the core.

In a multiprocessor environment, the processors need to communicate data with each other. The easiest method is to set up inter-processor communication through a mailbox. Mailbox features a bi-directional communication channel between two processors. This document contains information about the AXI4 version of the core.

In a multi-processor environment, the processors share common resources. The Mutex core provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource. This document contains information about the AXI4 version of the core.

The AXI Master Lite is an AXI4-compatible LogiCORE™ IP product. It provides an interface between a user-created IP core and an AXI4-Lite interface. The AXI4-Lite Master IP supports AXI4-Lite compatible bus mastering operations which are single 32-bit wide read or write data transfers.

The AXI Master Lite is an AXI4-compatible LogiCORE™ IP product. It provides an interface between a user-created IP core and an AXI4-Lite interface. The AXI4-Lite Master IP supports AXI4-Lite compatible bus mastering operations which are single 32-bit wide read or write data transfers.

The AXI Master Burst is a continuation of the Xilinx family of AXI4-compatible LogiCORE™ IP products. It provides a bidirectional interface between a User IP core and the AXI4 interface standard. This version of the AXI Master Burst has been optimized for bus mastering operations consisting of burst transactions. This document contains information about the AXI4 version of the core.