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| Date | Name |
|---|---|
| 12/14/2010 | LogiCORE IP System Monitor Wizard v2.1 Data Sheet(PDF, ver 2.1, 141 KB )
The LogiCORE™ IP System Monitor Wizard simplifies the instantiation of the System Monitor into the design in Virtex®-5 and Virtex-6 FPGAs. The Wizard creates an HDL file (Verilog or VHDL) that instantiates and configures the System Monitor to customer requirements. |
| 12/14/2010 | LogiCORE IP System Monitor Wizard v2.1 Getting Started Guide(PDF, ver 2.1, 1.39 MB )
The LogiCORE™ IP System Monitor Wizard Getting Started Guide describes the function and operation of the Xilinx® LogiCORE IP System Monitor Wizard in the Virtex®-5 LX/LXT/SXT sub-families, Virtex-6 LXT/SXT/HXT sub-families, lower-power Virtex-6 devices, and Virtex-5Q and Virtex-6Q defense grade devices. |
| Date | Name |
|---|---|
| 03/01/2011 | LogiCORE IP XADC Wizard v1.2 User Guide(PDF, ver 1.0, 2.12 MB )
The LogiCORE™ IP XADC Wizard User Guide describes the function and operation of the Xilinx® LogiCORE IP XADC Wizard in Xilinx Kintex™-7, and Virtex®-7 FPGA devices. |
| 08/31/2011 | LogiCORE IP XADC Wizard v1.3 User Guide(PDF, ver 1.2, 1.46 MB )
The LogiCORE™ IP XADC Wizard User Guide describes the function and operation of the Xilinx® LogiCORE IP XADC Wizard in Xilinx Kintex™-7, and Virtex®-7 FPGA devices. |
| 01/18/2012 | LogiCORE IP XADC Wizard v1.4 User Guide(PDF, ver 1.3, 1.69 MB )
The XADC Wizard is a Xilinx® CORE Generator™ tool that generates Verilog or VHDL Register Transfer Level (RTL) source code to configure the XADC primitive in Xilinx 7 Series FPGA devices. An example design and simulation test bench demonstrate how to integrate the core into user designs. |
| 04/24/2012 | LogiCORE IP XADC Wizard v2.1 User Guide(PDF, ver 1.4, 1.51 MB )
The XADC Wizard is a Xilinx® CORE Generator™ tool that generates Verilog or VHDL Register Transfer Level (RTL) source code to configure the XADC primitive in Xilinx 7 Series FPGA devices. An example design and simulation test bench demonstrate how to integrate the core into user designs. |