FIFO

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FIFO Generator

Date	Name
03/01/2011	LogiCORE IP FIFO Generator v8.1 Data Sheet (AXI)(PDF, ver 15.0, 1.19 MB ) The Xilinx LogiCORE&tradel; IP FIFO Generator is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
03/01/2011	LogiCORE IP FIFO Generator v8.1 User Guide (AXI)(PDF, ver 15.0, 4.91 MB ) The LogiCORE™ IP FIFO Generator User Guide describes the function and operation of the FIFO generator, as well as information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
06/22/2011	LogiCORE IP FIFO Generator v8.2 Data Sheet (AXI)(PDF, ver 16.0, 1.2 MB ) The Xilinx LogiCORE™ IP FIFO Generator is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
06/22/2011	LogiCORE IP FIFO Generator v8.2 User Guide (AXI)(PDF, ver 16.0, 5.22 MB ) The LogiCORE™ IP FIFO Generator User Guide describes the function and operation of the FIFO generator, as well as information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
10/19/2011	LogiCORE IP FIFO Generator v8.3 Data Sheet (AXI)(PDF, ver 17.0, 1.18 MB ) The Xilinx LogiCORE™ IP FIFO Generator is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
10/19/2011	LogiCORE IP FIFO Generator v8.3 User Guide (AXI)(PDF, ver 17.0, 5.25 MB ) The LogiCORE™ IP FIFO Generator User Guide describes the function and operation of the FIFO generator, as well as information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
10/19/2011	XAPP992 - FIFO Generator Migration Guide (AXI)(PDF, ver 10.0, 510 KB ) The FIFO Generator Migration Guide provides step-by-step instructions for migrating existing designs containing instances of legacy FIFO cores (Synchronous FIFO v5.x and Asynchronous FIFO v6.x) to the latest version of the FIFO Generator. This document contains information about the AXI4 version of the core. Design File(s): xapp992.zip Was this document helpful? Yes \| No
01/18/2012	LogiCORE IP FIFO Generator v8.4 Data Sheet (AXI)(PDF, ver 18.0, 1.23 MB ) The Xilinx LogiCORE™ IP FIFO Generator is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
01/18/2012	LogiCORE IP FIFO Generator v8.4 User Guide (AXI)(PDF, ver 18.0, 5.59 MB ) The LogiCORE™ IP FIFO Generator User Guide describes the function and operation of the FIFO generator, as well as information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
04/24/2012	LogiCORE IP FIFO Generator v9.1 Data Sheet (AXI)(PDF, ver 19.0, 1.21 MB ) The Xilinx LogiCORE™ IP FIFO Generator is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
04/24/2012	LogiCORE IP FIFO Generator v9.1 User Guide (AXI)(PDF, ver 19.0, 5.42 MB ) The LogiCORE™ IP FIFO Generator User Guide describes the function and operation of the FIFO generator, as well as information about designing, customizing, and implementing the core. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No

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