MIG

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MIG

Date	Name

09/23/2011	XAPP739 - AXI Multi-Ported Memory Controller(application/x-download, ver 1.0, 15.56 MB ) This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool. Design File(s): xapp739_axi_mpmc.zip Was this document helpful? Yes \| No
11/08/2011	MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4 and 13.1 This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.61 released in ISE Design Suite 12.4 and 13.1 for Virtex-5 and older families. This Answer Record contains the following information: General Information Software Requirements New Features Resolved Issues Known Issues For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf Was this document helpful? Yes \| No
01/18/2012	Spartan-6 FPGA Memory Interface Solutions User Guide (AXI)(PDF, ver 1.6, 4.78 MB ) This document describes the design tool flow and debug procedures for external memory interfaces implemented with the memory controller block in Spartan®-6 FPGAs. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
01/18/2012	Virtex-6 FPGA Memory Interface Solutions User Guide (AXI)(PDF, ver 1.10, 17.18 MB ) The Virtex-6 FPGA Memory Interface Solutions User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR2 or DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II memory interface cores for the Virtex®-6 FPGA. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
01/18/2012	Virtex-6 FPGA Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.10, 356 KB ) The Virtex®-6 FPGA memory interface solutions cores provide high-performance connections to DDR3 and DDR2 SDRAMs, QDRII+ SRAM, and RLDRAM II devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
01/18/2012	7 Series FPGAs Memory Interface Solutions User Guide (AXI)(PDF, ver 1.3, 11.3 MB ) This User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR3 SDRAM and QDRII+ SRAM memory interface cores for 7 series FPGAs. This document also describes an optional AXI4 interface. Was this document helpful? Yes \| No
01/18/2012	7 Series FPGAs Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.3, 340 KB ) The 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
10/19/2011	Spartan-6 FPGA Memory Interface Solutions User Guide (AXI)(PDF, ver 1.5, 5.47 MB ) This document describes the design tool flow and debug procedures for external memory interfaces implemented with the memory controller block in Spartan®-6 FPGAs. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
10/19/2011	Virtex-6 FPGA Memory Interface Solutions User Guide (AXI)(PDF, ver 1.9, 21.82 MB ) The Virtex-6 FPGA Memory Interface Solutions User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR2 or DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II memory interface cores for the Virtex®-6 FPGA. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
10/19/2011	Virtex-6 FPGA Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.9, 401 KB ) The Virtex®-6 FPGA memory interface solutions cores provide high-performance connections to DDR3 and DDR2 SDRAMs, QDRII+ SRAM, and RLDRAM II devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
10/19/2011	7 Series FPGAs Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.2, 355 KB ) The 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
10/19/2011	7 Series FPGAs Memory Interface Solutions User Guide (AXI)(PDF, ver 1.2, 10.33 MB ) This User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR3 SDRAM and QDRII+ SRAM memory interface cores for 7 series FPGAs. This document also describes an optional AXI4 interface. Was this document helpful? Yes \| No
06/22/2011	Spartan-6 FPGA Memory Interface Solutions User Guide (AXI)(PDF, ver 1.4, 6.82 MB ) This document describes the design tool flow and debug procedures for external memory interfaces implemented with the memory controller block in Spartan®-6 FPGAs. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
06/22/2011	Virtex-6 FPGA Memory Interface Solutions User Guide (AXI)(PDF, ver 1.8, 24.28 MB ) The Virtex-6 FPGA Memory Interface Solutions User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR2 or DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II memory interface cores for the Virtex®-6 FPGA. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
06/22/2011	Virtex-6 FPGA Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.8, 398 KB ) The Virtex®-6 FPGA memory interface solutions cores provide high-performance connections to DDR3 and DDR2 SDRAMs, QDRII+ SRAM, and RLDRAM II devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
06/22/2011	7 Series FPGAs Memory Interface Solutions User Guide (AXI)(PDF, ver 1.1, 13.25 MB ) This User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR3 SDRAM and QDRII+ SRAM memory interface cores for 7 series FPGAs. This document also describes an optional AXI4 interface. Was this document helpful? Yes \| No
06/22/2011	7 Series FPGAs Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.1, 350 KB ) The 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
03/01/2011	Virtex-6 FPGA Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.7, 356 KB ) The Virtex®-6 FPGA memory interface solutions core provides high-performance connections to DDR3 and DDR2 SDRAMs, QDR II+ SRAM, and RLDRAM II devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
03/01/2011	7 Series FPGAs Memory Interface Solutions Data Sheet (AXI)(PDF, ver 1.0, 215 KB ) The 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 SDRAM and QDRII+ SRAM devices. This document describes an optional AXI4 interface. Was this document helpful? Yes \| No
03/01/2011	Virtex-6 FPGA Memory Interface Solutions User Guide (AXI)(PDF, ver 1.7, 23.6 MB ) The Virtex®-6 FPGA Memory Interface Solutions User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR2 or DDR3 SDRAM, QDRII+ SRAM, and RLDRAM II memory interface cores for the Virtex-6 FPGA. This document contains information about the AXI4 version of the core. Was this document helpful? Yes \| No
03/01/2011	7 Series FPGAs Memory Interface Solutions User Guide (AXI)(PDF, ver 1.0, 6.8 MB ) This User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR3 SDRAM and QDRII+ SRAM memory interface cores for 7 series FPGAs. This document also describes an optional AXI4 interface. Was this document helpful? Yes \| No
09/21/2010	Memory Interface Solutions User Guide(PDF, ver 3.6, 14.88 MB ) The Memory Interface Generator (MIG) is a tool used to generate memory interfaces for Xilinx® FPGAs. Was this document helpful? Yes \| No
06/24/2010	MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.4 released in ISE Design Suite 12.1 and contains the following information: General Information Software Requirements New Features Resolved Issues Known Issues For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf Was this document helpful? Yes \| No

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