 Spartan-6 FPGA Memory Controller User Guide (PDF)
 View Document Details
This guide describes the Spartan®-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards. Was this document helpful? Yes | No
|
1.1 |
5.81 MB |
08/18/2009 |
Virtex-6 FPGA Memory Interface Solutions User Guide (PDF)
View Document Details The Virtex®-6 FPGA Memory Interface Solutions User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR2 or DDR3 SDRAM and QDR II+ SRAM memory interface cores for the Virtex-6 FPGA. Was this document helpful? Yes | No
|
|
17.27 MB |
09/16/2009 |
Virtex-6 FPGA Memory Interface Solutions Data Sheet (PDF)
View Document Details The Virtex®-6 FPGA memory interface solutions core provides high-performance connections to DDR3 and DDR2 SDRAMs, QDR II+ SRAM, and RLDRAM II devices. Was this document helpful? Yes | No
|
1.1 |
326 KB |
09/16/2009 |
Memory Interface Solutions User Guide (PDF)
View Document Details The Memory Interface Generator (MIG) is a tool used to generate memory interfaces for Xilinx® FPGAs. Was this document helpful? Yes | No
|
3.2 |
14.27 MB |
09/16/2009 |
 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
View Document Details Keywords: Design Advisory, 3.2
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. Was this document helpful? Yes | No
|
NA |
NA |
11/18/2009 |
DDR3、DDR2、DDR、Spartan-6 FPGA MCB、RLDRAMII、QDRII+、QDRII、DDRII コアを含んだ MIG のデザイン アドバイザリ
View Document Details キーワード : Design Advisory, 3.2, デザイン アドバイザリ, エンドポイント, PCI Express
デザイン アドバイザリ アンサーは、現在進行中のデザインに影響する重要な問題に対して作成され、ザイリンクス アラート通知システムに含められます。 Was this document helpful? Yes | No
|
NA |
NA |
11/18/2009 |
