RAM and ROM
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Single-Port Block Memory
| Date | Name |
|---|---|
| 04/28/2005 | Single-Port Block Memory Core v6.2 Data Sheet(PDF, ver 1.2, 1.55 MB )
This is a data sheet for Single-Port Block Memory Core v6.2. |
topDual Port Block Memory
| Date | Name |
|---|---|
| 08/31/2005 | Dual-Port Block Memory Core v6.3 Data Sheet(PDF, ver 1.3, 1.26 MB )
This is a data sheet for the Dual-Port Block Memory Core v6.3 core. |
Distributed Memory Generator
| Date | Name |
|---|---|
| 04/19/2010 | LogiCORE IP Distributed Memory Generator v5.1 Data Sheet(PDF, ver 12.0, 701 KB )
The Xilinx LogiCORE™ IP Distributed Memory Generator core uses Xilinx Synthesis Technology (XST) to create a variety of distributed memories. |
| 03/01/2011 | LogiCORE IP Distributed Memory Generator v6.1 Data Sheet(PDF, ver 13.0, 730 KB )
The Xilinx LogiCORE™ IP Distributed Memory Generator core uses Xilinx Synthesis Technology (XST) to create a variety of distributed memories. |
| 06/22/2011 | Distributed Memory Generator v6.2 Data Sheet(PDF, ver 14.0, 649 KB )
The Xilinx LogiCORE™ IP Distributed Memory Generator core uses Xilinx Synthesis Technology (XST) to create a variety of distributed memories. |
| 01/18/2012 | Distributed Memory Generator v6.3 Data Sheet(PDF, ver 15.0, 666 KB )
The Xilinx LogiCORE™ IP Distributed Memory Generator core uses Xilinx Synthesis Technology (XST) to create a variety of distributed memories. |
| 04/24/2012 | Distributed Memory Generator v7.1 Data Sheet(PDF, ver 16.0, 741 KB )
The Xilinx LogiCORE™ IP Distributed Memory Generator core uses Xilinx Synthesis Technology (XST) to create a variety of distributed memories. |
Block Memory Generator
| Date | Name |
|---|---|
| 03/01/2011 | LogiCORE IP Block Memory Generator v6.1, Data Sheet (AXI)(PDF, ver 15.0, 3.67 MB )
The Xilinx LogiCORE™ IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs. This document contains information about the AXI4 version of the core. |
| 06/22/2011 | LogiCORE IP Block Memory Generator v6.2 Data Sheet (AXI)(PDF, ver 16.0, 4.35 MB )
The Xilinx LogiCORE™ IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs. This document contains information about the AXI4 version of the core. |
| 06/22/2011 | XAPP917 - Block Memory Generator Migration Guide(PDF, ver 10.0, 569 KB )
This document provides step-by-step instructions for migrating designs containing instances of either the legacy Dual Port Block Memory and Single Port Block Memory LogiCORE™ IP cores or older versions of the LogiCORE IP Block Memory Generator core. Design File(s): |
| 01/18/2012 | LogiCORE IP Block Memory Generator v6.3 Data Sheet (AXI)(PDF, ver 17.0, 4.29 MB )
The Xilinx LogiCORE™ IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs. This document contains information about the AXI4 version of the core. |
| 04/24/2012 | LogiCORE IP Block Memory Generator v7.1 Data Sheet (AXI)(PDF, ver 18.0, 4.36 MB )
The Xilinx LogiCORE™ IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs. This document contains information about the AXI4 version of the core. |